Commit 03050f07 authored by Jan Pospisil's avatar Jan Pospisil

Independent Trigger Latency for the two channels (http://www.ohwr.org/issues/1389)

parent 3cdb7af8
......@@ -30,6 +30,8 @@
-- Revisions :
-- Date Version Author
-- 2016-08-24 1.0 Jan Pospisil
-- 2016-09-05 1.1 Jan Pospisil Independent Trigger Latency for the two
-- channels (issue 1389)
-------------------------------------------------------------------------------
library ieee;
......@@ -60,8 +62,10 @@ entity DelayedPulseGeneratorsCdc is
Ch2ResMemReadStrobe_o: out std_logic;
Overflow_ib16: in unsigned(15 downto 0);
OverflowLoad_i: in std_logic;
TriggerLatency_ib16: in unsigned(15 downto 0);
TriggerLatencyLoad_i: in std_logic;
Ch1TriggerLatency_ib16: in unsigned(15 downto 0);
Ch1TriggerLatencyLoad_i: in std_logic;
Ch2TriggerLatency_ib16: in unsigned(15 downto 0);
Ch2TriggerLatencyLoad_i: in std_logic;
Ch1Mode_i: in t_Mode;
Ch1Running_o: out std_logic;
Ch2Mode_i: in t_Mode;
......@@ -81,7 +85,8 @@ end entity;
architecture syn of DelayedPulseGeneratorsCdc is
signal Overflow_b_slv, OverflowRf_b_slv: std_logic_vector(Overflow_ib16'range) := (others => '0');
signal TriggerLatency_b_slv, TriggerLatencyRf_b_slv: std_logic_vector(TriggerLatency_ib16'range) := (others => '0');
signal Ch1TriggerLatency_b_slv, Ch1TriggerLatencyRf_b_slv: std_logic_vector(Ch1TriggerLatency_ib16'range) := (others => '0');
signal CH2TriggerLatency_b_slv, Ch2TriggerLatencyRf_b_slv: std_logic_vector(Ch2TriggerLatency_ib16'range) := (others => '0');
signal Ch1Mode_slv, Ch1ModeRf_slv: std_logic_vector(1 downto 0);
signal Ch1ModeLoad: std_logic;
signal Ch2Mode_slv, Ch2ModeRf_slv: std_logic_vector(1 downto 0);
......@@ -93,7 +98,8 @@ architecture syn of DelayedPulseGeneratorsCdc is
signal Ch1RunningRf: std_logic;
signal Ch2RunningRf: std_logic;
signal OverflowRf_b: unsigned(Overflow_ib16'range);
signal TriggerLatencyRf_b: unsigned(TriggerLatency_ib16'range);
signal Ch1TriggerLatencyRf_b: unsigned(Ch1TriggerLatency_ib16'range);
signal Ch2TriggerLatencyRf_b: unsigned(Ch2TriggerLatency_ib16'range);
signal Ch1ModeRf: t_Mode;
signal Ch1ModeLoadRf: std_logic;
signal Ch2ModeRf: t_Mode;
......@@ -147,21 +153,37 @@ begin
OverflowRf_b <= unsigned(OverflowRf_b_slv);
-- TriggerLatency
-- Ch1TriggerLatency
TriggerLatency_b_slv <= std_logic_vector(TriggerLatency_ib16);
Ch1TriggerLatency_b_slv <= std_logic_vector(Ch1TriggerLatency_ib16);
cTriggerLatencySyncer: entity work.RegSyncer(syn)
cCh1TriggerLatencySyncer: entity work.RegSyncer(syn)
port map (
ClkIn_ik => Clk_ik,
ClkOut_ik => ClkRf_ik,
Data_ib => TriggerLatency_b_slv,
Load_i => TriggerLatencyLoad_i,
Data_ob => TriggerLatencyRf_b_slv,
Data_ib => Ch1TriggerLatency_b_slv,
Load_i => Ch1TriggerLatencyLoad_i,
Data_ob => Ch1TriggerLatencyRf_b_slv,
Load_o => open
);
TriggerLatencyRf_b <= unsigned(TriggerLatencyRf_b_slv);
Ch1TriggerLatencyRf_b <= unsigned(Ch1TriggerLatencyRf_b_slv);
-- Ch2TriggerLatency
Ch2TriggerLatency_b_slv <= std_logic_vector(Ch2TriggerLatency_ib16);
cCh2TriggerLatencySyncer: entity work.RegSyncer(syn)
port map (
ClkIn_ik => Clk_ik,
ClkOut_ik => ClkRf_ik,
Data_ib => Ch2TriggerLatency_b_slv,
Load_i => Ch2TriggerLatencyLoad_i,
Data_ob => Ch2TriggerLatencyRf_b_slv,
Load_o => open
);
Ch2TriggerLatencyRf_b <= unsigned(Ch2TriggerLatencyRf_b_slv);
-- Ch1Mode
......@@ -218,7 +240,7 @@ begin
Clk_ik => ClkRf_ik,
Reset_ir => ResetRf_r,
Overflow_ib16 => OverflowRf_b,
TriggerLatency_ib16 => TriggerLatencyRf_b,
TriggerLatency_ib16 => Ch1TriggerLatencyRf_b,
Mode_i => Ch1ModeRf,
ModeLoad_i => Ch1ModeLoadRf,
SetMemAddress_ob11 => Ch1SetMemAddress_ob11,
......@@ -239,7 +261,7 @@ begin
Clk_ik => ClkRf_ik,
Reset_ir => ResetRf_r,
Overflow_ib16 => OverflowRf_b,
TriggerLatency_ib16 => TriggerLatencyRf_b,
TriggerLatency_ib16 => Ch2TriggerLatencyRf_b,
Mode_i => Ch2ModeRf,
ModeLoad_i => Ch2ModeLoadRf,
SetMemAddress_ob11 => Ch2SetMemAddress_ob11,
......
......@@ -35,6 +35,8 @@
-- 2016-08-24 1.0 Jan Pospisil
-- 2016-09-01 1.1 Jan Pospisil added version numbers (major.minor.rev)
-- added clock_stable status bit
-- 2016-09-05 1.2 Jan Pospisil Independent Trigger Latency for the two
-- channels (issue 1389)
-------------------------------------------------------------------------------
library ieee;
......@@ -226,8 +228,10 @@ begin
Ch2ResMemReadStrobe_o => Ch2ResMemReadStrobe,
Overflow_ib16 => WbRegsOutput.overflow_o,
OverflowLoad_i => WbRegsOutput.overflow_load_o,
TriggerLatency_ib16 => WbRegsOutput.trigger_latency_o,
TriggerLatencyLoad_i => WbRegsOutput.trigger_latency_load_o,
Ch1TriggerLatency_ib16 => WbRegsOutput.ch1_trigger_latency_o,
Ch1TriggerLatencyLoad_i => WbRegsOutput.ch1_trigger_latency_load_o,
Ch2TriggerLatency_ib16 => WbRegsOutput.ch2_trigger_latency_o,
Ch2TriggerLatencyLoad_i => WbRegsOutput.ch2_trigger_latency_load_o,
Ch1Mode_i => f_SlvToMode(WbRegsOutput.control_ch1_mode_o),
Ch1Running_o => WbRegsInput.status_channel_1_running_i,
Ch2Mode_i => f_SlvToMode(WbRegsOutput.control_ch2_mode_o),
......
......@@ -30,6 +30,8 @@
-- Revisions :
-- Date Version Author
-- 2016-08-24 1.0 Jan Pospisil
-- 2016-09-05 1.1 Jan Pospisil Independent Trigger Latency for the two
-- channels (issue 1389)
-------------------------------------------------------------------------------
library ieee;
......@@ -80,7 +82,8 @@ architecture syn of WbSlaveWrapper is
signal ch2_delay_reset: unsigned(9 downto 0) := (others => '0');
signal trigger_threshold: unsigned(15 downto 0) := (others => '0');
signal overflow: unsigned(15 downto 0) := (others => '0');
signal trigger_latency: unsigned(15 downto 0) := (others => '0');
signal ch1_trigger_latency: unsigned(15 downto 0) := (others => '0');
signal ch2_trigger_latency: unsigned(15 downto 0) := (others => '0');
-- delayed load signals for LOAD_EXT fields
signal vcxo_voltage_load: std_logic := '0';
signal clock_ratio_m1_load: std_logic := '0';
......@@ -90,7 +93,8 @@ architecture syn of WbSlaveWrapper is
signal ch2_delay_reset_load: std_logic := '0';
signal trigger_threshold_load: std_logic := '0';
signal overflow_load: std_logic := '0';
signal trigger_latency_load: std_logic := '0';
signal ch1_trigger_latency_load: std_logic := '0';
signal ch2_trigger_latency_load: std_logic := '0';
begin
......@@ -141,7 +145,8 @@ begin
ch2_delay_reset_load <= '0';
trigger_threshold_load <= '0';
overflow_load <= '0';
trigger_latency_load <= '0';
ch1_trigger_latency_load <= '0';
ch2_trigger_latency_load <= '0';
vcxo_voltage <= (others => '0');
clock_ratio_m1 <= (others => '0');
......@@ -151,7 +156,8 @@ begin
ch2_delay_reset <= (others => '0');
trigger_threshold <= (others => '0');
overflow <= (others => '0');
trigger_latency <= (others => '0');
ch1_trigger_latency <= (others => '0');
ch2_trigger_latency <= (others => '0');
else
vcxo_voltage_load <= '0';
clock_ratio_m1_load <= '0';
......@@ -161,7 +167,8 @@ begin
ch2_delay_reset_load <= '0';
trigger_threshold_load <= '0';
overflow_load <= '0';
trigger_latency_load <= '0';
ch1_trigger_latency_load <= '0';
ch2_trigger_latency_load <= '0';
if WbRegsOutput.vcxo_voltage_load_o = '1' then
vcxo_voltage <= WbRegsOutput.vcxo_voltage_o;
......@@ -195,9 +202,13 @@ begin
overflow <= WbRegsOutput.overflow_o;
overflow_load <= '1';
end if;
if WbRegsOutput.trigger_latency_load_o = '1' then
trigger_latency <= WbRegsOutput.trigger_latency_o;
trigger_latency_load <= '1';
if WbRegsOutput.ch1_trigger_latency_load_o = '1' then
ch1_trigger_latency <= WbRegsOutput.ch1_trigger_latency_o;
ch1_trigger_latency_load <= '1';
end if;
if WbRegsOutput.ch2_trigger_latency_load_o = '1' then
ch2_trigger_latency <= WbRegsOutput.ch2_trigger_latency_o;
ch2_trigger_latency_load <= '1';
end if;
end if;
end if;
......@@ -205,7 +216,7 @@ begin
pInputRegisters: process (
WbRegs_i,
vcxo_voltage, clock_ratio_m1, ch1_delay_set, ch1_delay_reset, ch2_delay_set, ch2_delay_reset, trigger_threshold, overflow, trigger_latency
vcxo_voltage, clock_ratio_m1, ch1_delay_set, ch1_delay_reset, ch2_delay_set, ch2_delay_reset, trigger_threshold, overflow, ch1_trigger_latency, ch2_trigger_latency
) is begin
-- #!@& ISE doesn't know VHDL 2008 (... process (all) ...)
-- by default, all values are passed
......@@ -219,13 +230,14 @@ begin
WbRegsInput.ch2_delay_reset_i <= ch2_delay_reset;
WbRegsInput.trigger_threshold_i <= trigger_threshold;
WbRegsInput.overflow_i <= overflow;
WbRegsInput.trigger_latency_i <= trigger_latency;
WbRegsInput.ch1_trigger_latency_i <= ch1_trigger_latency;
WbRegsInput.ch2_trigger_latency_i <= ch2_trigger_latency;
end process;
pOutputRegisters: process (
WbRegsOutput,
vcxo_voltage, clock_ratio_m1, ch1_delay_set, ch1_delay_reset, ch2_delay_set, ch2_delay_reset, trigger_threshold, overflow, trigger_latency,
vcxo_voltage_load, clock_ratio_m1_load, ch1_delay_set_load, ch1_delay_reset_load, ch2_delay_set_load, ch2_delay_reset_load, trigger_threshold_load, overflow_load, trigger_latency_load
vcxo_voltage, clock_ratio_m1, ch1_delay_set, ch1_delay_reset, ch2_delay_set, ch2_delay_reset, trigger_threshold, overflow, ch1_trigger_latency, ch2_trigger_latency,
vcxo_voltage_load, clock_ratio_m1_load, ch1_delay_set_load, ch1_delay_reset_load, ch2_delay_set_load, ch2_delay_reset_load, trigger_threshold_load, overflow_load, ch1_trigger_latency_load, ch2_trigger_latency_load
) is begin
-- #!@& ISE doesn't know VHDL 2008 (... process(all) ...)
-- by default, all values are passed
......@@ -239,7 +251,8 @@ begin
WbRegs_o.ch2_delay_reset_o <= ch2_delay_reset;
WbRegs_o.trigger_threshold_o <= trigger_threshold;
WbRegs_o.overflow_o <= overflow;
WbRegs_o.trigger_latency_o <= trigger_latency;
WbRegs_o.ch1_trigger_latency_o <= ch1_trigger_latency;
WbRegs_o.ch2_trigger_latency_o <= ch2_trigger_latency;
WbRegs_o.vcxo_voltage_load_o <= vcxo_voltage_load;
WbRegs_o.clock_ratio_m1_load_o <= clock_ratio_m1_load;
......@@ -249,7 +262,8 @@ begin
WbRegs_o.ch2_delay_reset_load_o <= ch2_delay_reset_load;
WbRegs_o.trigger_threshold_load_o <= trigger_threshold_load;
WbRegs_o.overflow_load_o <= overflow_load;
WbRegs_o.trigger_latency_load_o <= trigger_latency_load;
WbRegs_o.ch1_trigger_latency_load_o <= ch1_trigger_latency_load;
WbRegs_o.ch2_trigger_latency_load_o <= ch2_trigger_latency_load;
end process;
end architecture;
\ No newline at end of file
......@@ -190,7 +190,7 @@ peripheral {
};
reg {
name = "CH1 SET delay configuration";
name = "SET delay configuration (channel 1)";
prefix = "ch1_delay_set";
description = "10 bit fine delay for pulse generation - delay of the SET pulse, i.e. CH1 pulse delay";
......@@ -206,7 +206,7 @@ peripheral {
};
reg {
name = "CH1 RES delay configuration";
name = "RES delay configuration (channel 1)";
prefix = "ch1_delay_reset";
description = "10 bit fine delays for pulse generation - delay of the RES pulse, i.e. CH1 pulse width";
......@@ -221,7 +221,7 @@ peripheral {
};
reg {
name = "CH2 SET delay configuration";
name = "SET delay configuration (channel 2)";
prefix = "ch2_delay_set";
description = "10 bit fine delay for pulse generation - delay of the SET pulse, i.e. CH2 pulse delay";
......@@ -237,7 +237,7 @@ peripheral {
};
reg {
name = "CH2 RES delay configuration";
name = "RES delay configuration (channel 2)";
prefix = "ch2_delay_reset";
description = "10 bit fine delays for pulse generation - delay of the RES pulse, i.e. CH2 pulse width";
......@@ -282,9 +282,9 @@ peripheral {
};
reg {
name = "Trigger latency";
prefix = "trigger_latency";
description = "The latency of the trigger in number of clock cycles of the serial stream clock. When trigger is received, serial stream memory pointer is set to this value.";
name = "Trigger latency (channel 1)";
prefix = "ch1_trigger_latency";
description = "The latency of the trigger in number of clock cycles of the serial stream clock, for channel 1. When trigger is received, serial stream memory pointer is set to this value.";
field {
name = "Trigger latency value";
......@@ -357,6 +357,21 @@ peripheral {
};
};
reg {
name = "Trigger latency (channel 2)";
prefix = "ch2_trigger_latency";
description = "The latency of the trigger in number of clock cycles of the serial stream clock, for channel 2. When trigger is received, serial stream memory pointer is set to this value.";
field {
name = "Trigger latency value";
type = UNSIGNED;
size = 16;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
ram {
name = "CH1 SET serial stream";
prefix = "ch1_set_mem";
......
......@@ -39,6 +39,8 @@
## better configuration; better debugging;
## comments; attempt for better trigger
## latency calibration (not working yet)
## 2016-09-05 1.3 Jan Pospisil Independent Trigger Latency for the two
## channels (issue 1389)
##-----------------------------------------------------------------------------
# TODO: proper BUSY bits checking
......@@ -613,7 +615,8 @@ def Calibrate(phaseOffset):
globalFineOffset = 0
(bitOffset, fineOffset) = CalculateParams(phaseOffset)
print('bitOffset = '+str(bitOffset)+', fineOffset = '+str(fineOffset))
WbWrite('trig_latency', bitOffset)
WbWrite('ch1_trig_latency', bitOffset) # TODO: separate calibration for each channel
WbWrite('ch2_trig_latency', bitOffset)
globalFineOffset = fineOffset
Init()
......
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