Commit 6a062568 authored by Jan Pospisil's avatar Jan Pospisil

added patches used on submodules during developement of v1.0

parent 88165e5d
From 01823282d75316cee707c186f175877ad347a047 Mon Sep 17 00:00:00 2001
From: Jan Pospisil <j.pospisil@cern.ch>
Date: Wed, 24 Aug 2016 11:52:48 +0200
Subject: [PATCH 2/7] added assignments to (new) unspecified WB signals
---
modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd | 1 +
modules/wishbone/wb_i2c_master/wb_i2c_master.vhd | 3 +++
modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd | 3 +++
modules/wishbone/wb_spi/wb_spi.vhd | 3 +++
modules/wishbone/wb_spi/xwb_spi.vhd | 2 ++
5 files changed, 12 insertions(+)
diff --git a/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd b/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
index eae3c49..88272b2 100644
--- a/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
+++ b/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
@@ -213,4 +213,5 @@ begin
end if;
end process;
+ slave_o.int <= '0'; -- TODO: not implemented
end rtl;
diff --git a/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd b/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd
index f32f2c9..2f21579 100644
--- a/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd
+++ b/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd
@@ -149,6 +149,9 @@ begin
wb_out.dat(7 downto 0) <= dat_out;
wb_out.dat(wb_out.dat'left downto 8) <= (others => '0');
+ wb_out.err <= '0';
+ wb_out.rty <= '0';
+ wb_out.stall <= '0';
end rtl;
diff --git a/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd b/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
index dab5a96..7ff5bb4 100644
--- a/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
+++ b/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
@@ -80,5 +80,8 @@ begin -- rtl
sda_pad_i => sda_pad_i,
sda_pad_o => sda_pad_o,
sda_padoen_o => sda_padoen_o);
+
+ slave_o.err <= '0';
+ slave_o.rty <= '0';
end rtl;
diff --git a/modules/wishbone/wb_spi/wb_spi.vhd b/modules/wishbone/wb_spi/wb_spi.vhd
index b31d8a6..138d9a1 100644
--- a/modules/wishbone/wb_spi/wb_spi.vhd
+++ b/modules/wishbone/wb_spi/wb_spi.vhd
@@ -127,4 +127,7 @@ begin
mosi_pad_o => pad_mosi_o,
miso_pad_i => pad_miso_i);
+ wb_out.rty <= '0';
+ wb_out.stall <= '0';
+
end rtl;
diff --git a/modules/wishbone/wb_spi/xwb_spi.vhd b/modules/wishbone/wb_spi/xwb_spi.vhd
index e54b370..5df78c5 100644
--- a/modules/wishbone/wb_spi/xwb_spi.vhd
+++ b/modules/wishbone/wb_spi/xwb_spi.vhd
@@ -85,5 +85,7 @@ begin
pad_sclk_o => pad_sclk_o,
pad_mosi_o => pad_mosi_o,
pad_miso_i => pad_miso_i);
+
+ slave_o.rty <= '0';
end rtl;
--
2.8.1.windows.1
From c2437b99ee27da7db69a8e14d611ed62921e3ab5 Mon Sep 17 00:00:00 2001
From: Jan Pospisil <j.pospisil@cern.ch>
Date: Wed, 24 Aug 2016 11:53:55 +0200
Subject: [PATCH 3/7] removed synchronous reset from sensitivity lists
---
modules/common/gc_serial_dac.vhd | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/modules/common/gc_serial_dac.vhd b/modules/common/gc_serial_dac.vhd
index e8f50b4..f01fd10 100644
--- a/modules/common/gc_serial_dac.vhd
+++ b/modules/common/gc_serial_dac.vhd
@@ -120,7 +120,7 @@ begin
iValidValue <= load_i;
- process(clk_i, rst_n_i)
+ process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
@@ -153,7 +153,7 @@ begin
end process;
- process(clk_i, rst_n_i)
+ process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
@@ -170,7 +170,7 @@ begin
end if;
end process;
- process(clk_i, rst_n_i)
+ process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
--
2.8.1.windows.1
From 2a81efe1cff9ea8182084a8e4f3e5b4fd74d079b Mon Sep 17 00:00:00 2001
From: Jan Pospisil <j.pospisil@cern.ch>
Date: Wed, 24 Aug 2016 11:56:54 +0200
Subject: [PATCH 4/7] added ASYNC_REG attribute for better timing
analysis/simulation in Xilinx tools
---
modules/common/gc_sync_register.vhd | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/modules/common/gc_sync_register.vhd b/modules/common/gc_sync_register.vhd
index c237e87..72736ef 100644
--- a/modules/common/gc_sync_register.vhd
+++ b/modules/common/gc_sync_register.vhd
@@ -28,6 +28,11 @@ architecture rtl of gc_sync_register is
attribute keep of sync0 : signal is "true";
attribute keep of sync1 : signal is "true";
+ attribute async_reg : string;
+ attribute async_reg of gc_sync_register_in : signal is "true";
+ attribute async_reg of sync0 : signal is "true";
+ attribute async_reg of sync1 : signal is "true";
+
begin
process(clk_i, rst_n_a_i)
--
2.8.1.windows.1
From 1d5568120cab0208ad14b4fc72f402f1f44974cb Mon Sep 17 00:00:00 2001
From: Jan Pospisil <j.pospisil@cern.ch>
Date: Wed, 24 Aug 2016 11:57:45 +0200
Subject: [PATCH 5/7] added default values; typos
---
modules/wishbone/wb_onewire_master/sockit_owm.v | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/modules/wishbone/wb_onewire_master/sockit_owm.v b/modules/wishbone/wb_onewire_master/sockit_owm.v
index d815f64..6d3b5c6 100644
--- a/modules/wishbone/wb_onewire_master/sockit_owm.v
+++ b/modules/wishbone/wb_onewire_master/sockit_owm.v
@@ -81,7 +81,7 @@ module sockit_owm #(
parameter T_BITS_O = (BTP_O == "1.0") ? 2 : 3, // bit sample
parameter T_RCVR_O = (BTP_O == "1.0") ? 2 : 4, // recovery
parameter T_IDLE_O = (BTP_O == "1.0") ? 96 : 192, // idle timer
- // clock divider ratios (defaults are for a 2MHz clock)
+ // clock divider ratios (defaults are for a 1MHz clock)
parameter CDR_N = 5-1, // normal mode
parameter CDR_O = 1-1 // overdrive mode
)(
@@ -143,8 +143,8 @@ wire [PDW-1:0] bus_rdt_pwr_sel;
// clock divider
reg [CDW-1:0] div;
-reg [CDW-1:0] cdr_n;
-reg [CDW-1:0] cdr_o;
+reg [CDW-1:0] cdr_n = CDR_N[CDW-1:0];
+reg [CDW-1:0] cdr_o = CDR_O[CDW-1:0];
wire pls;
// cycle control and status
@@ -416,7 +416,7 @@ end
// IO
//////////////////////////////////////////////////////////////////////////////
-// only one 1-wire line cn be accessed at the same time
+// only one 1-wire line can be accessed at the same time
assign owr_e = owr_oen << owr_sel;
// all 1-wire lines can be powered independently
assign owr_p = owr_pwr;
--
2.8.1.windows.1
From 386d137346c58f94ee52e0212151c1ea64b1e112 Mon Sep 17 00:00:00 2001
From: Jan Pospisil <j.pospisil@cern.ch>
Date: Wed, 24 Aug 2016 11:59:26 +0200
Subject: [PATCH 6/7] propagated CDR_N/O generics up the hierarchy; added
assignments to (new) unspecified WB signals
---
.../wishbone/wb_onewire_master/wb_onewire_master.vhd | 17 ++++++++++++++---
.../wishbone/wb_onewire_master/xwb_onewire_master.vhd | 12 +++++++++---
2 files changed, 23 insertions(+), 6 deletions(-)
diff --git a/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd b/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
index 933c2c8..b56e54d 100644
--- a/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
+++ b/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
@@ -37,7 +37,9 @@ entity wb_onewire_master is
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_ports : integer := 1;
g_ow_btp_normal : string := "5.0";
- g_ow_btp_overdrive : string := "1.0"
+ g_ow_btp_overdrive : string := "1.0";
+ g_CDR_N : integer := 4; -- normal mode
+ g_CDR_O : integer := 0 -- overdrive mode
);
port (
@@ -69,7 +71,9 @@ architecture rtl of wb_onewire_master is
generic(
BTP_N : string;
BTP_O : string;
- OWN : integer);
+ OWN : integer;
+ CDR_N : integer;
+ CDR_O : integer);
port(
clk : in std_logic;
@@ -153,7 +157,9 @@ begin -- rtl
generic map (
BTP_N => g_ow_btp_normal,
BTP_O => g_ow_btp_overdrive,
- OWN => g_num_ports)
+ OWN => g_num_ports,
+ CDR_N => g_CDR_N,
+ CDR_O => g_CDR_O)
port map (
clk => clk_sys_i,
rst => rst,
@@ -166,5 +172,10 @@ begin -- rtl
owr_p => owr_pwren_o,
owr_e => owr_en_o,
owr_i => owr_i);
+
+ adp_in.err <= '0';
+ adp_in.rty <= '0';
+ adp_in.stall <= '0';
+
end rtl;
diff --git a/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd b/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
index 78e2b56..31b11d1 100644
--- a/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
+++ b/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
@@ -9,7 +9,9 @@ entity xwb_onewire_master is
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_ports : integer := 1;
g_ow_btp_normal : string := "5.0";
- g_ow_btp_overdrive : string := "1.0"
+ g_ow_btp_overdrive : string := "1.0";
+ g_CDR_N : integer := 4; -- normal mode
+ g_CDR_O : integer := 0 -- overdrive mode
);
port(
@@ -37,7 +39,9 @@ architecture rtl of xwb_onewire_master is
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_ports : integer;
g_ow_btp_normal : string;
- g_ow_btp_overdrive : string);
+ g_ow_btp_overdrive : string;
+ g_CDR_N : integer;
+ g_CDR_O : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
@@ -66,7 +70,9 @@ begin -- rtl
g_address_granularity => g_address_granularity,
g_num_ports => g_num_ports,
g_ow_btp_normal => g_ow_btp_normal,
- g_ow_btp_overdrive => g_ow_btp_overdrive)
+ g_ow_btp_overdrive => g_ow_btp_overdrive,
+ g_CDR_N => g_CDR_N,
+ g_CDR_O => g_CDR_O)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
--
2.8.1.windows.1
From d2851d70988a845fbe8c66039fb00711c53df669 Mon Sep 17 00:00:00 2001
From: Jan Pospisil <j.pospisil@cern.ch>
Date: Wed, 24 Aug 2016 16:07:53 +0200
Subject: [PATCH 1/6] commented out unused code
---
hdl/vme64x-core/rtl/VME64xCore_Top.vhd | 6 +++---
hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd | 4 ++--
hdl/vme64x-core/rtl/VME_bus.vhd | 18 +++++++++++-------
3 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/hdl/vme64x-core/rtl/VME64xCore_Top.vhd b/hdl/vme64x-core/rtl/VME64xCore_Top.vhd
index e50fde9..d884ab7 100755
--- a/hdl/vme64x-core/rtl/VME64xCore_Top.vhd
+++ b/hdl/vme64x-core/rtl/VME64xCore_Top.vhd
@@ -220,8 +220,8 @@ architecture RTL of VME64xCore_Top is
signal s_FIFOreset : std_logic;
signal s_VME_DATA_IRQ : std_logic_vector(31 downto 0);
signal s_VME_DATA_VMEbus : std_logic_vector(31 downto 0);
- signal s_VME_DATA_b : std_logic_vector(31 downto 0);
- signal s_fifo : std_logic;
+ -- signal s_VME_DATA_b : std_logic_vector(31 downto 0);
+ -- signal s_fifo : std_logic;
signal s_VME_DTACK_VMEbus : std_logic;
signal s_VME_DTACK_IRQ : std_logic;
signal s_VME_DTACK_OE_VMEbus : std_logic;
@@ -256,7 +256,7 @@ architecture RTL of VME64xCore_Top is
-- Oversampled input signals
signal VME_RST_n_oversampled : std_logic;
signal VME_AS_n_oversampled : std_logic;
- signal VME_AS_n_oversampled1 : std_logic; -- for the IRQ_Controller
+ --signal VME_AS_n_oversampled1 : std_logic; -- for the IRQ_Controller
--signal VME_LWORD_n_oversampled : std_logic;
signal VME_WRITE_n_oversampled : std_logic;
signal VME_DS_n_oversampled : std_logic_vector(1 downto 0);
diff --git a/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd b/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
index e03ab3e..7cc86a2 100644
--- a/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
+++ b/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
@@ -180,7 +180,7 @@ architecture Behavioral of VME_CR_CSR_Space is
signal s_locDataIn : unsigned(7 downto 0);
signal s_CrCsrOffsetAderIndex : unsigned(18 downto 0);
signal s_odd_parity : std_logic;
- signal s_BARerror : std_logic;
+ --signal s_BARerror : std_logic;
signal s_BAR_o : std_logic_vector(4 downto 0);
--===========================================================================
-- Architecture begin
@@ -193,7 +193,7 @@ s_odd_parity <= VME_GA_oversampled(5) xor VME_GA_oversampled(4) xor
-- If the crate is not driving the GA lines or the parity is even the BAR register
-- is set to 0x00 and the following flag is asserted; the board will not answer if the
-- master accesses its CR/CSR space and we can see a time out error in the VME bus.
-s_BARerror <= not(s_BAR_o(4) or s_BAR_o(3)or s_BAR_o(2) or s_BAR_o(1) or s_BAR_o(0));
+--s_BARerror <= not(s_BAR_o(4) or s_BAR_o(3)or s_BAR_o(2) or s_BAR_o(1) or s_BAR_o(0));
--------------------------------------------------------------------------------
s_CR_Space <= f_set_CR_space(g_BoardID, g_CRspace, g_ManufacturerID, g_RevisionID, g_ProgramID);
-- CR
diff --git a/hdl/vme64x-core/rtl/VME_bus.vhd b/hdl/vme64x-core/rtl/VME_bus.vhd
index c7b78e6..c86fc29 100755
--- a/hdl/vme64x-core/rtl/VME_bus.vhd
+++ b/hdl/vme64x-core/rtl/VME_bus.vhd
@@ -183,11 +183,12 @@ architecture RTL of VME_bus is
signal s_locAddrBeforeOffset : unsigned(63 downto 0);
signal s_phase1addr : unsigned(63 downto 0); -- for 2e transfers
signal s_phase2addr : unsigned(63 downto 0); --
- signal s_phase3addr : unsigned(63 downto 0); --
+ -- signal s_phase3addr : unsigned(63 downto 0); --
signal s_addrOffset : unsigned(17 downto 0); -- block transfers|
signal s_CrCsrOffsetAddr : unsigned(18 downto 0); -- CR/CSR address
signal s_DataShift : unsigned(5 downto 0);
- signal s_2eLatchAddr : std_logic_vector(1 downto 0); -- for 2e transfers
+ -- uncomment if 2e is implemented:
+ --signal s_2eLatchAddr : std_logic_vector(1 downto 0); -- for 2e transfers
signal s_locDataSwap : std_logic_vector(63 downto 0);
signal s_locDataInSwap : std_logic_vector(63 downto 0);
signal s_locDataOutWb : std_logic_vector(63 downto 0);
@@ -230,9 +231,10 @@ architecture RTL of VME_bus is
signal s_transferActive : std_logic; -- active VME transfer
-- signal s_retry : std_logic; -- RETRY signal
signal s_retry_out : std_logic;
- signal s_berr : std_logic; -- BERR signal
- signal s_berr_1 : std_logic; --
- signal s_berr_2 : std_logic; --
+ -- uncomment if 2e is implemented:
+ --signal s_berr : std_logic; -- BERR signal
+ -- signal s_berr_1 : std_logic; -- -- uncomment if 2e is implemented:
+ -- signal s_berr_2 : std_logic; -- -- uncomment if 2e is implemented:
-- Access decode signals
signal s_confAccess : std_logic; -- Asserted when CR or CSR is addressed
@@ -442,9 +444,11 @@ begin
s_dataToOutput <= s_FSM.s_dataToOutput;
s_dataToAddrBus <= s_FSM.s_dataToAddrBus;
s_transferActive <= s_FSM.s_transferActive;
- s_2eLatchAddr <= s_FSM.s_2eLatchAddr;
+ -- uncomment if 2e is implemented:
+ --s_2eLatchAddr <= s_FSM.s_2eLatchAddr;
s_retry_out <= s_FSM.s_retry;
- s_berr <= s_FSM.s_berr;
+ -- uncomment if 2e is implemented:
+ --s_berr <= s_FSM.s_berr;
s_BERR_out <= s_FSM.s_BERR_out;
p_VMEmainFSM : process(clk_i)
--
2.8.1.windows.1
From 806dab30876fa827f037a03838c58182ad3576b1 Mon Sep 17 00:00:00 2001
From: Jan Pospisil <j.pospisil@cern.ch>
Date: Wed, 24 Aug 2016 16:09:41 +0200
Subject: [PATCH 2/6] added default values for determined start-up state
---
hdl/vme64x-core/rtl/VME64xCore_Top.vhd | 4 ++--
hdl/vme64x-core/rtl/VME_Init.vhd | 16 ++++++++--------
hdl/vme64x-core/rtl/VME_bus.vhd | 22 +++++++++++-----------
3 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/hdl/vme64x-core/rtl/VME64xCore_Top.vhd b/hdl/vme64x-core/rtl/VME64xCore_Top.vhd
index d884ab7..a569d90 100755
--- a/hdl/vme64x-core/rtl/VME64xCore_Top.vhd
+++ b/hdl/vme64x-core/rtl/VME64xCore_Top.vhd
@@ -264,8 +264,8 @@ architecture RTL of VME64xCore_Top is
signal VME_GA_oversampled : std_logic_vector(5 downto 0);
signal VME_IACK_n_oversampled : std_logic;
signal VME_IACKIN_n_oversampled : std_logic;
- signal s_reg_1 : std_logic_vector(1 downto 0);
- signal s_reg_2 : std_logic_vector(1 downto 0);
+ signal s_reg_1 : std_logic_vector(1 downto 0) := (others => '0');
+ signal s_reg_2 : std_logic_vector(1 downto 0) := (others => '0');
--===========================================================================
-- Architecture begin
--===========================================================================
diff --git a/hdl/vme64x-core/rtl/VME_Init.vhd b/hdl/vme64x-core/rtl/VME_Init.vhd
index 8a47598..e9ae38b 100644
--- a/hdl/vme64x-core/rtl/VME_Init.vhd
+++ b/hdl/vme64x-core/rtl/VME_Init.vhd
@@ -80,9 +80,9 @@ end VME_Init;
--===========================================================================
architecture Behavioral of VME_Init is
- signal s_initReadCounter : unsigned(8 downto 0);
+ signal s_initReadCounter : unsigned(8 downto 0) := to_unsigned(0, InitReadCount_o'length);
signal s_initState : t_initState;
- signal s_latchCRdata : std_logic; -- Stores read CR data
+ signal s_latchCRdata : std_logic := '0'; -- Stores read CR data
signal s_initInProgress : std_logic;
signal s_CRadd_offset : unsigned(18 downto 0);
signal s_CRaddr_base : unsigned(18 downto 0);
@@ -92,12 +92,12 @@ architecture Behavioral of VME_Init is
signal s_FUNC_ADEM : t_FUNC_32b_array;
signal s_FUNC_AMCAP : t_FUNC_64b_array;
signal s_FUNC_XAMCAP : t_FUNC_256b_array;
- signal s_BEG_USER_CSR : unsigned(23 downto 0);
- signal s_END_USER_CSR : unsigned(23 downto 0);
- signal s_BEG_USER_CR : unsigned(23 downto 0);
- signal s_END_USER_CR : unsigned(23 downto 0);
- signal s_BEG_CRAM : unsigned(23 downto 0);
- signal s_END_CRAM : unsigned(23 downto 0);
+ signal s_BEG_USER_CSR : unsigned(23 downto 0) := (others => '0');
+ signal s_END_USER_CSR : unsigned(23 downto 0) := (others => '0');
+ signal s_BEG_USER_CR : unsigned(23 downto 0) := (others => '0');
+ signal s_END_USER_CR : unsigned(23 downto 0) := (others => '0');
+ signal s_BEG_CRAM : unsigned(23 downto 0) := (others => '0');
+ signal s_END_CRAM : unsigned(23 downto 0) := (others => '0');
--===========================================================================
-- Architecture begin
diff --git a/hdl/vme64x-core/rtl/VME_bus.vhd b/hdl/vme64x-core/rtl/VME_bus.vhd
index c86fc29..5bbb8de 100755
--- a/hdl/vme64x-core/rtl/VME_bus.vhd
+++ b/hdl/vme64x-core/rtl/VME_bus.vhd
@@ -89,7 +89,7 @@ entity VME_bus is
-- VME signals
VME_RST_n_i : in std_logic;
VME_AS_n_i : in std_logic;
- VME_LWORD_n_o : out std_logic;
+ VME_LWORD_n_o : out std_logic := '0';
VME_LWORD_n_i : in std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
@@ -100,11 +100,11 @@ entity VME_bus is
VME_DTACK_OE_o : out std_logic;
VME_BERR_o : out std_logic;
VME_ADDR_i : in std_logic_vector(31 downto 1);
- VME_ADDR_o : out std_logic_vector(31 downto 1);
+ VME_ADDR_o : out std_logic_vector(31 downto 1) := (others => '0');
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
VME_DATA_i : in std_logic_vector(31 downto 0);
- VME_DATA_o : out std_logic_vector(31 downto 0);
+ VME_DATA_o : out std_logic_vector(31 downto 0) := (others => '0');
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
@@ -149,10 +149,10 @@ entity VME_bus is
Endian_i : in std_logic_vector(2 downto 0);
Sw_Reset : in std_logic;
BAR_i : in std_logic_vector(4 downto 0);
- numBytes : out std_logic_vector(12 downto 0);
- transfTime : out std_logic_vector(39 downto 0);
+ numBytes : out std_logic_vector(12 downto 0) := (others => '0'); -- TODO: what's this?
+ transfTime : out std_logic_vector(39 downto 0) := (others => '0'); -- TODO: what's this?
-- Debug
- leds : out std_logic_vector(7 downto 0)
+ leds : out std_logic_vector(7 downto 0) := (others => '0') -- not used
);
end VME_bus;
--===========================================================================
@@ -181,11 +181,11 @@ architecture RTL of VME_bus is
signal s_locAddr, s_rel_locAddr : unsigned(63 downto 0); -- Local address
signal s_locAddr2e : unsigned(63 downto 0); -- for 2e transfers
signal s_locAddrBeforeOffset : unsigned(63 downto 0);
- signal s_phase1addr : unsigned(63 downto 0); -- for 2e transfers
- signal s_phase2addr : unsigned(63 downto 0); --
+ signal s_phase1addr : unsigned(63 downto 0) := (others => '0'); -- for 2e transfers
+ signal s_phase2addr : unsigned(63 downto 0) := (others => '0'); --
-- signal s_phase3addr : unsigned(63 downto 0); --
signal s_addrOffset : unsigned(17 downto 0); -- block transfers|
- signal s_CrCsrOffsetAddr : unsigned(18 downto 0); -- CR/CSR address
+ signal s_CrCsrOffsetAddr : unsigned(18 downto 0) := (others => '0'); -- CR/CSR address
signal s_DataShift : unsigned(5 downto 0);
-- uncomment if 2e is implemented:
--signal s_2eLatchAddr : std_logic_vector(1 downto 0); -- for 2e transfers
@@ -196,9 +196,9 @@ architecture RTL of VME_bus is
-- Latched signals
signal s_VMEaddrLatched : unsigned(63 downto 1); --Latch on AS falling edge
signal s_LWORDlatched : std_logic; -- Stores LWORD on falling edge of AS
- signal s_DSlatched : std_logic_vector(1 downto 0); -- Stores DS
+ signal s_DSlatched : std_logic_vector(1 downto 0) := (others => '0'); -- Stores DS
signal s_AMlatched : std_logic_vector(5 downto 0); --Latch on AS f. edge
- signal s_XAM : unsigned(7 downto 0); -- Stores received XAM
+ signal s_XAM : unsigned(7 downto 0) := (others => '0'); -- Stores received XAM -- TODO: what's this?
-- Type of data transfer (depending on VME_DS_n, VME_LWORD_n and VME_ADDR(1))
signal s_typeOfDataTransfer : t_typeOfDataTransfer;
--
2.8.1.windows.1
From bbcfafaa2add9fbf18dcfbb08f5269a93863deae Mon Sep 17 00:00:00 2001
From: Jan Pospisil <j.pospisil@cern.ch>
Date: Wed, 24 Aug 2016 16:11:41 +0200
Subject: [PATCH 3/6] added default (error) return value
---
hdl/vme64x-core/rtl/vme64x_pack.vhd | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hdl/vme64x-core/rtl/vme64x_pack.vhd b/hdl/vme64x-core/rtl/vme64x_pack.vhd
index 5f96db2..50a3ee6 100644
--- a/hdl/vme64x-core/rtl/vme64x_pack.vhd
+++ b/hdl/vme64x-core/rtl/vme64x_pack.vhd
@@ -852,7 +852,8 @@ package body vme64x_pack is
if (8*I >= width) then
return(I);
end if;
- end loop;
+ end loop;
+ return -1;
end function f_div8;
function f_log2_size (A : natural) return natural is
--
2.8.1.windows.1
From 50becf03fb51a8710e585234b8bcc6416d1d990a Mon Sep 17 00:00:00 2001
From: Jan Pospisil <j.pospisil@cern.ch>
Date: Wed, 24 Aug 2016 16:12:11 +0200
Subject: [PATCH 4/6] fixed typo (address <-> data)
---
hdl/vme64x-core/rtl/xvme64x_core.vhd | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hdl/vme64x-core/rtl/xvme64x_core.vhd b/hdl/vme64x-core/rtl/xvme64x_core.vhd
index 3fb1f62..39375f3 100644
--- a/hdl/vme64x-core/rtl/xvme64x_core.vhd
+++ b/hdl/vme64x-core/rtl/xvme64x_core.vhd
@@ -128,7 +128,7 @@ architecture wrapper of xvme64x_core is
CYC_o : out std_logic;
ERR_i : in std_logic;
RTY_i : in std_logic;
- SEL_o : out std_logic_vector(f_div8(g_wb_addr_width) - 1 downto 0);
+ SEL_o : out std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
STB_o : out std_logic;
ACK_i : in std_logic;
WE_o : out std_logic;
--
2.8.1.windows.1
From 747c6060db995421441a38a0ead5d02137f00328 Mon Sep 17 00:00:00 2001
From: Jan Pospisil <j.pospisil@cern.ch>
Date: Wed, 24 Aug 2016 16:20:05 +0200
Subject: [PATCH 5/6] added modification notices
---
hdl/vme64x-core/rtl/VME64xCore_Top.vhd | 5 +++++
hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd | 4 ++++
hdl/vme64x-core/rtl/VME_Init.vhd | 4 ++++
hdl/vme64x-core/rtl/VME_bus.vhd | 5 +++++
hdl/vme64x-core/rtl/vme64x_pack.vhd | 4 ++++
hdl/vme64x-core/rtl/xvme64x_core.vhd | 4 ++++
6 files changed, 26 insertions(+)
diff --git a/hdl/vme64x-core/rtl/VME64xCore_Top.vhd b/hdl/vme64x-core/rtl/VME64xCore_Top.vhd
index a569d90..df983b9 100755
--- a/hdl/vme64x-core/rtl/VME64xCore_Top.vhd
+++ b/hdl/vme64x-core/rtl/VME64xCore_Top.vhd
@@ -80,6 +80,11 @@
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
+-- Modifications:
+-- 2016-08-24: by Jan Pospisil (j.pospisil@cern.ch)
+-- * commented out unused code
+-- * added default values for determined start-up state
+--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
diff --git a/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd b/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
index 7cc86a2..76250dc 100644
--- a/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
+++ b/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
@@ -99,6 +99,10 @@
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
+-- Modifications:
+-- 2016-08-24: by Jan Pospisil (j.pospisil@cern.ch)
+-- * commented out unused code
+--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
diff --git a/hdl/vme64x-core/rtl/VME_Init.vhd b/hdl/vme64x-core/rtl/VME_Init.vhd
index e9ae38b..dacfe89 100644
--- a/hdl/vme64x-core/rtl/VME_Init.vhd
+++ b/hdl/vme64x-core/rtl/VME_Init.vhd
@@ -13,6 +13,10 @@
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 11/2012
-- Version v0.03
+--______________________________________________________________________________
+-- Modifications:
+-- 2016-08-24: by Jan Pospisil (j.pospisil@cern.ch)
+-- * added default values for determined start-up state
--________________________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
diff --git a/hdl/vme64x-core/rtl/VME_bus.vhd b/hdl/vme64x-core/rtl/VME_bus.vhd
index 5bbb8de..74778a9 100755
--- a/hdl/vme64x-core/rtl/VME_bus.vhd
+++ b/hdl/vme64x-core/rtl/VME_bus.vhd
@@ -55,6 +55,11 @@
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
+-- Modifications:
+-- 2016-08-24: by Jan Pospisil (j.pospisil@cern.ch)
+-- * commented out unused code
+-- * added default values for determined start-up state
+--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
diff --git a/hdl/vme64x-core/rtl/vme64x_pack.vhd b/hdl/vme64x-core/rtl/vme64x_pack.vhd
index 50a3ee6..e019a0b 100644
--- a/hdl/vme64x-core/rtl/vme64x_pack.vhd
+++ b/hdl/vme64x-core/rtl/vme64x_pack.vhd
@@ -10,6 +10,10 @@
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 11/2012
-- Version v0.03
+--______________________________________________________________________________
+-- Modifications:
+-- 2016-08-24: by Jan Pospisil (j.pospisil@cern.ch)
+-- * added default (error) return value
--_______________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
diff --git a/hdl/vme64x-core/rtl/xvme64x_core.vhd b/hdl/vme64x-core/rtl/xvme64x_core.vhd
index 39375f3..2c17367 100644
--- a/hdl/vme64x-core/rtl/xvme64x_core.vhd
+++ b/hdl/vme64x-core/rtl/xvme64x_core.vhd