tuned RF clock sense

3801c470 · Jan Pospisil · 473d43a5 · 3801c470
Commit 3801c470 authored Aug 23, 2016 by Jan Pospisil
Hide whitespace changes
Inline Side-by-side

Showing with 1 addition and 1 deletion

FfpgSlave.vhd hdl/ffpg/rtl/FfpgSlave.vhd +1 -1

No files found.
--- a/hdl/ffpg/rtl/FfpgSlave.vhd
+++ b/hdl/ffpg/rtl/FfpgSlave.vhd
@@ -310,7 +310,7 @@ begin
        generic map (
            g_ClkFrequency => g_ClkFrequency,
            g_SenseFrequencyWidth => WbRegsInput.frequency_i'length,
-            g_SenseFrequencyStableCount => 4,
+            g_SenseFrequencyStableCount => 3,
            g_SenseFrequencyStableWidth => 10
        )
        port map (