AFC v4.0
Milestone ID: 12
Rationale
AFC v3.1 turned up to be a versatile, cost-effective FMC-HPC carrier. During years since the last release, a number of bugs were revealed and different ideas have raised how to make a design more useful and attract a wide range of users. This release aims to address outstanding issues and make AFC compatible with Sinara hardware ecosystem and ARTIQ control system which opens a way to quantum applications.
Project organization
The main executive of this upgrade is Warsaw University of Technology with @tprzywoz as an electronics designer and @msowinski for project management and consultancy.
Project is divided into several phases:
- current project state diagnosis, selection of issues to be applied and parts of the project to be revised,
- release of the initial version of schematics to be discussed with the community,
- community consultations,
- release of the final schematics to be approved by the community,
- schematics review,
- release of the PCB layout,
- layout review,
- production of prototypes,
- project roundup.
After phase 5 is completed an agreed entity (Creotech?) can start the upgrade of openMMC according to the instructions provided by WUT so that it is ready when prototypes arrive.
All consultations and review processes will take place on OHWR in the form of issues and comments to these.
Schedule and current status
Please be aware that the following schedule may be subject to change!
Action that is currently taking place is emphasised with bold font.
Date | Action |
---|---|
4.05.2020 | Start of the project. |
11.05.2020 | Start of phase 1. |
27.05.2020 | Release of the schematics to be discussed with community and begging of community consultations. |
7.06.2020 | End of community consultations. |
10.06.2020 | Release of the final schematics to be approved by community |
15.06.2020 | Start of design schematics review. |
19.06.2020 | End of design schematics review. |
10.07.2020 | Release of the PCB layout. |
13.07.2020 | Start of design layout review. |
17.07.2020 | End of design layout review. |
20.07.2020 | Start of prototype fabrication and project roundup. |
23.07.2020 | End of project roundup, waiting for prototypes. |
TBD | Prototypes arrival and testing. |
- AFC v4.0 PI verification
- Recommended PCB stackup
- TCK is pulled up and down
- FPGA TMS pullup is unnececary
- FMC CLK_DIR - pull-down and usage
- Connect PROGRAM_B to I/O extender
- Out-of-standard designators
- TCLKs seem to be purposely DC-coupled
- Swapped FMC MGT clocks
- Check if U.FL connectors muxed with AMC port 0 by optional mounting are still useful
- Add a pull-down resistor in the ADBUS7 pin (FT4232H-56Q)
- Clocks polarity on 8V54816A
- Remove connector J3 from CPU
- FMC CLK_DIR not connected
- Connect FMC I2C pull-up resistors to FMC_3P3VAUX
- Move MCP23016 to different I2C interface
- Remove non-existent banks of XC7A200T in schematics
- VADJ translators
- FT4232H USB UART / JTAG Improvements
- Make sure PCIe links are stable in the long term
- Suggestions for improving schematics readability
- Check if external WR clock input option is still useful
- Independent control of Si571 oscillators
- Improve names of nets connected to RTM connector
- Check if implemented D1.3 RTM pinout is truly compatible with MTCA.4.1
- Remove option to route PORT 3 to FPGA I/O pins
- FCLK_GTP216_CLK0_P is duplicated and _N signal is missing
- Prevent MMC resets when opening terminal for controlling serial ports on Linux
- Remove voltage translators for the M-LVDS inputs
- FMC Powergood to FPGA
- Enable SPI communication between FMC and FPGA
- Change pussh button S1 for shorter version
- Support ETM tracing for MMC [CPU.SchDoc]
- Fixed clock source pin assignement
- Define basic assembly variants
- Make sure LNLS Timing design will work with AFCv4
- Make sure LNLS BPM design will work with AFCv4
- Check for EOL components
- Simplify SATA circuit
- Verify if PCB thickness complies with AMC standard
- Make sure WR will work
- Make sure DRTIO will work
- Remove MMC access to FPGA flash
- Check if additional memory is required for MMC upgrade
- Goldpin connectors
- WR circuit
- Implement inrush current limit
- AFC v4 Upgrade
- VCXO 20 MHz (BOOT_CLK_IN) is connected to incompatible FPGA bank
- FLASH memory stops responding after some time
- Reroute JP1 JTAG connector pins to match vendor defaults
- Level Translator TXB0104PWR
- Reformat EEPROM access circuit
- Change JP1 connector to a shrouded version
- Change JP2 connector to a more usual one
- Standardize library to generate clean BOM
- M-LVDS bus is not transparent to FPGA configuration
- Better folder and file structure
- Write assembly variant to EEPROM
- Battery holder height
- modify I2C bus structure
- JTAG: missing TVS diode for TDO pin
- Clocking scheme redesign
- Move current measurement closer to the PSUs
- Change either RTM_PS# or EN_I2C_RTM pins on LPC so one can be output while the other is an input
- Change MMC from LPC1764 to 1768
- Add extra INA220 to 12V rail to check presence of crate power
- Change flash memory form M25P to N25Q
- Change SCANSTA111 to SCANSTA112
- Pullup or latch DCDC enable lines to allow payload to stay on in case of MMC reset
- Replace D5 and D6 for a single higher forward current diode
- Payload power line stays at ~2.5V when disabled
- Add test points for power supplies and ground posts
- Use internal XADC reference
- AMC #ENABLE signal should reset MMC According to AMC specification
- Wrong I2C pullups on IPMB
- Disconnect PCIE_CLK1 from one of GTP 216 inputs
- Possible conflict on I2C mux
- RTM_MP should be connected via a key
- Add INA220 monitor to RTM_PWR line
- SDRAM ICs MT41K512 are outdated
- Fix JTAG signals to comply with uTCA spec.
- RTM mechanical key should be connected to SHIELD instead of GND
- 1V2 DC/DC wrong compensation value (R44)
- components in fmc region3
- PLL DAC1/DAC2 SYNC_N are swapped
- Remove IC67A (ATMega)
- Fix clk20_vcxo routing