WR circuit

We're planning to implement WRCLK circuit based on 2x Si571 and remove CDCM61004. Is everybody OK with that?

@danielot

mentioned in issue #22 (closed)

We are rather agnostic about White Rabbit circuitry since our applications do not rely on it (yet). As a general comment, we see good value in keeping up with what has been done for other boards at CERN. During our last meeting with Creotech and WUT @Greg has mentioned someone (I guess @twlostow) was replacing the VCXO by a DCXO and this could be done for the AFC as well. Do you have updates on this?

I have consulted @twlostow on that and he agreed that 2xSi571 + 2x dedicated DAC will be OK. However, I'd feel much more comfortable if @twlostow goes through the schematics.

Sorry for the lack of knowledge, but what is the use for 2xSi571? Why not only one? I'm not much knowledgeable on White Rabbit.

one is for clock recovery, one is for helper oscillator needed for phase detector

So, one would go to the clock switch and the other straight to the FPGA?

yes

Is there a specific clock region that will always be used by this clock? Or we must place it in a MRCC input? I'm currently looking for a pin to place this clock so that we may still keep a fixed, always available 20MHz clock for the logic.

I think @gustavo.bruno question got outdated as we'll have 125 MHz fixed clock.

@tprzywoz Maybe it would be more clear if instead of single OSC3 / OSC4 components two variants get their respective components (Si570 / Si571). It will also lead to a more clear BOM.

It won't affect BOM if we proper configure variants. But I agree that schematics will be more clear so I will add it in next commit.

added schematics label

mentioned in issue #124 (closed)

mentioned in commit 9098d25e

Sorry I missed this before, I didn't got the notification from the answers after me, I got some problems with my mail two weeks ago.

I just noticed the extra schematics symbols. I don't think they make the sheets clearer - I actually believe they make it harder to understand, with the extra derivations on the nets that are needed. I actually didn't, and thought at first why there were two oscillators in parallel. It also may make layout and verification harder, specially if we are going to overlap their footprints.

My suggestion is to use the proper Altium variant feature, which guarantees that there won't be two overlapping items by mistake in the BOM. To make the variant presence more clear, a note on the schematics may also help, even adding in which case the user should choose each variant.

I deleted Si571 (second OSC). It will be added as a variant as described in #124 (closed).

mentioned in commit 0d87a553

closed

This is just a final check. I noticed that the more stable Si570 oscillator (Si570BBC, 20 ppm temp. stability) is connected to the clock crossbar while the less stable (Si570CAC, 50 ppm) is directly connected to the FPGA.

I just wondered whether this is the optimal configuration for White Rabbit. I must admit I have no knowledge to make this evaluation. I just wanted to check it because I remember @Greg being explicit that one of the WR clocks should necessarily go straight to the FPGA and I had the impression this should the more stable one.

One of the DCXO/VCXO is helper oscillator. It needs to go to the FPGA generalIO or clock capable input. It is not critical in terms of jitter. It can go via mux.

I see. For v4 this is the current situation:

• OSC1 Si570BBC - LVDS output, 20 ppm temp. stability, connected to clock crossbar
• OSC2 Si570CAC - CMOS output, 50 ppm temp. stability, connected to MRCC FPGA pin

OSC2 seems ok to be used as helper clock from Greg's description.

What about OSC1? Is it ok to have it going through the crossbar?

reopened

Hi all,

If you're going to use Si570's, please take these two things into account:

• if the oscillator is to be controlled by the WR SoftPLL over I2C, it must have a dedicated I2C bus connected to dedicated FPGA pins. I2C muxes on the way will not work, the speed of the interface is barely enough to keep it locked to WR and there's no bandwidth left for anything else on the I2C bus connected to the Si57x
• consider using a Si571 adjusted by a DAC. This is much easier to handle in the WR Core.

Hi Tom. I ended up adding some noise into this conversation when I mentioned Si570, sorry for that.

For WR configuration there's indeed the provision to mount Si571 VCXOs. This is managed by an assembly variant.

The 2 conditions you listed are already completely satisfied in the proposed v4.

I think the main open question now is whether the clock coming from the main WR oscillator, in this case a Si571 with LVDS output, can go through the crossbar switch 8V54816A (while the helper Si571 is CMOS and enters direclty to a CC FPGA pin).

Do you believe the jitter degradation caused by the clock crossbar will be relevant to the overall performance of the WR endpoint?

Taking advantage of this: @tprzywoz, @msowinski maybe it is worth adding a note saying that despite SI570 is displayed by default, there is an assembly option allowing for Si571 assembly.

This will make it less confusing for who is looking at the PDF.

@danielot Definitely adding a note is a good idea. The more clear the schematics are, the better. Regarding the connection of OSC1 (WR Main) to the crossbar - from my understanding, it is crucial for WR application. This way you can distribute precise WR clock to various endpoints (e.g. FMC, RTM, FPGA) without adding FPGA jitter.

I see, thanks for clarifying. So, in other terms, the jitter which will be added by the 8V54816A is negligible for the WR purposes.

closed