modify I2C bus structure

apply i2c bus structure as in attached file

Files

• i2c_bus.pdf

I applied Sinara's solution: two parallel TCA9548ARGER (check I2C_MUX.SchDoc).

Outputs:

1. Temp. sensors
2. RTCE
3. Not used
4. Power monitors
5. RTM
6. FMC2
7. FMC1

mentioned in issue #17 (closed)

changed milestone to %AFC v4.0

This solution is proven to work in several projects (Sayma, Metlino, Kasli). Are we happy with that?

assigned to @tprzywoz and unassigned @Greg

Noone objects. Solved in 3eabfde6

closed

Sorry for not pointing this before, but while reviewing the MMC, we noticed that the I2C between FPGA and MMC is still there, which seems to be different from the proposal of having separate muxes for FPGA and MMC. These are the signals FPGA_SDA and FPGA_SCL. We at LNLS agreed that removing them will make the I2C bus more straigthforward.

As an extra, we may also remove the voltage translator IC25 if we accept that the I2C bus will only be guaranteed accessible for Vadj of at least 1.8V, which is the minimum level for TCA9548ARGER (notice that the current translator allows for a minimum of 1.5V, so not much loss).

reopened

mentioned in issue #148 (closed)

I think it's OK to disconnect FPGA I2C from MMC. Especially that we do have a SPI communication channel.

I'd also suggest disconnecting MUX2 (where power control is connected) from FPGA I2C mux so that user application can not mangle with power supply. Or just connect to the freed MMC ports.

MMC disconnected from FPGA I2C.

mentioned in commit d351ca72

closed