PLL DAC1/DAC2 SYNC_N are swapped
Look at IC41 in Clock_management.SchDoc. DAC1_SYNC_N/DAC2_SYNC_N are mixed at the level translator pins.
Look at IC41 in Clock_management.SchDoc. DAC1_SYNC_N/DAC2_SYNC_N are mixed at the level translator pins.
No child items are currently assigned. Use child items to break down this issue into smaller parts.
Link issues together to show that they're related. Learn more.
changed milestone to %AFC v4.0
closed
Solved by c961a747