Disconnect PCIE_CLK1 from one of GTP 216 inputs

This connection is completely redundant and unnecessary.
In artix 7 clock input can be shared between horizontally adjacent GTP (IIRC 116,216 and 113,213), so we could it for example to LINK01

Let me try to put it another way, to see if I understand the proposal. It surely relates to #1425:

The proposed new clock tree has 3 signals coming from the switch to a MGT - MGT113, 116 and 213. MGT216 would receive FCLKA directly from the backplane.

Merging both issues, we would have only two (116 and 216, for example) connections from the switch to the FPGA. FCLKA would be routed to the clock switch, so it could be used by the MGT for PICe.

116 and 216 can share clocks because they are both in the top half, so it's more useful to use e.g. 213, 216.

GTP 113 (or 213) definitely would need to have 125 MHz available (via switch or directly), as it's most likely to be used for GbE (10 GbE in 4x2.5G mode).

assigned to @tprzywoz

changed milestone to %AFC v4.0

Disconnected

Solved in c961a747. For clocking tree discussion see #43 (closed)

closed