Mock Turtle is an HDL core of a generic control system node, based on a deterministic multicore CPU architecture. Mock Turtle can use White Rabbit as the means of communication and synchronization in a distributed system. More info at the Wiki page

OHR project where you can get help and guidelines about OHR. It's a support project for questions/feedback and bugs. More info at the Wiki page

The TimIQ system is an IQ modulator allowing to phase shift a radio frequency clock with a resolution of 40 fs and an accuracy of 8 ps. Software.

The TimIQ system is an IQ modulator allowing to phase shift a radio frequency clock with a resolution of 40 fs and an accuracy of 8 ps. Hardware.

The High Performance WR Receiver module is an MTCA eRTM (slots 14-15) WR receiver with redundant uplinks, providing a variety of ultra-low jitter clock signals.

More info at the Wiki page

Hardware design of the PandABox. Includes schematics, PCB layout and manufacturing files.

White Rabbit is a fully deterministic Ethernet-based network for general purpose data transfer and synchronization. It can synchronize over 1000 nodes with sub-ns accuracy over fiber lengths of up to 10 km. Commercially available. More info at the Wiki page

A system to characterize large area silicon pad sensors with several hundred channels. This repository contains the microcontroller firmware.

Gateware (HDL design) for FMC ADC 100M 14b 4cha on SPEC and SVEC carriers.

A system to characterise large area silicon pad sensors with several hundred channels. It consists of two PCBs. One is an active switching 512-to-1 matrix. The second one is a passive probe card to contact the sensor. Testing.

A Trigger/Timing Logic Unit designed for use with High Energy Physics beam-tests. Provides a simple and flexible interface for fast timing and triggering signals at the AIDA pixel sensor beam-telescope. Connects to a FPGA carrier card via a FMC connector.

( N.B. Use the sub-project Git repositories, not the top level repository )

White Rabbit Trigger Distribution project. More info at the Wiki page

A simple VME64x carrier for two low pin count FPGA Mezzanine Cards (VITA 57). It has memory and clocking resources and supports the White Rabbit timing and control network. Commercially available. More info at the Wiki page

CompactRIO module with White Rabbit functionality. LabVIEW support, front-panel connector with 10 I/O lines.

More info at the Wiki page

A system to characterise large area silicon pad sensors with several hundred channels. It consists of two PCBs. One is an active switching 512-to-1 matrix. The second one is a passive probe card to contact the sensor. Hardware.

FPGA Firmware ( "Gateware" ) for AIDA-2020 TLU and AIDA mini-TLU

Uses "IPBus Build" ( ipbb )

Build instructions at Instructions here

DDR3 controller with two pipelined Wishbone slave ports. It is based on the Spartan6 hardware core and a management core generated by Xilinx CoreGen.

Distribution of clock signals over a White Rabbit network. It uses an PLL with a numerically controlled (DDS) oscillator to extract the characteristics of a signal that in turn are distributed over a White Rabbit network to receiving nodes with a DAC that regenerate exactly the same signal in phase. More info at the Wiki page

Production and functional tests for fmc-dac-600m-12b-1cha-dds