Gateware (HDL design) for FMC ADC 100M 14b 4cha on SPEC and SVEC carriers.

A simple 4-lane PCIe carrier for a low pin count FPGA Mezzanine Card (VITA 57). It supports the White Rabbit timing and control network. Commercially available. Linux and Labview drivers available for some mezzanine cards. More info at the Wiki page

A bridge between the local bus of the Gennum GN4124 (PCIe to local bus bridge) and Wishbone.

A collection of cores needed in the White Rabbit node and switch. Includes White Rabbit PTP Core (WRPC).

A collection of platform-independent cores such as memories, synchronizer circuits and Wishbone cores.

More info at the Wiki page

VentilatorPAL is a high-quality and low-cost, open source ventilator. More info at the Wiki page

DI/OT Zynq Ultrascale-based System Board with White Rabbit support. More info at the Wiki page

A meta project used to discuss and present information about Open Hardware and related subjects. More info at the Wiki page More info about the CERN Open Hardware licence More info about the OHR.org site support

A simple VME64x carrier for two low pin count FPGA Mezzanine Cards (VITA 57). It has memory and clocking resources and supports the White Rabbit timing and control network. Commercially available. More info at the Wiki page

This project covers the hardware development of the White Rabbit switch.

A project devoted to developing and discussing the CERN Open Hardware Licence. More info at the Wiki page

Rules for low-level software to check an FPGA for sanity, to ease debugging and to provide support for low-level software auto-configuration for byte-order and optional components. More info at Wiki

A simple 4-lane PCIe carrier for a FPGA Mezzanine Card (VITA 57). It supports the White Rabbit timing and control network. More info at the Wiki page

A simple VME64x carrier for two high pin count FPGA Mezzanine Cards (VITA 57). It has memory and clocking resources and supports the White Rabbit timing and control network. Follow-up of SVEC.

FmcDIO5chTTLa is a 5-bit port digital IO card in FMC form-factor. Each single-bit port can be configured individually as input or output. The I/Os on LEMO 00 connectors are TTL compatible. Commercially available. More info at the Wiki page

Tool for generating multi-purpose makefiles for FPGA projects.

Main features:

makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefiles

Hdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page

Gateware (HDL design) for FMC TDC 1ns 5cha on SPEC and SVEC carriers.

White Rabbit PTP Core software for LatticeMico32. It consists of a software wrapper for running a PTP daemon without an operating system and device drivers for WRPC HDL internals.

OHR project where you can get help and guidelines about OHR. It's a support project for questions/feedback and bugs. More info at the Wiki page

This project contains all the HDL gateware necessary for the FPGA of the WR switch.