Commits · 689cba916a0bfa16d8ae1716b9fd462d3372e068 · Projects / FMC DEL 1ns 2cha · Open Hardware Repository

17 Aug, 2016 3 commits
- added bunch-wise configuration possibility · 689cba91
  Jan Pospisil authored Aug 17, 2016
  
  689cba91
- added missing port assignment · 36aac099
  Jan Pospisil authored Aug 17, 2016
  
  36aac099
- added AD9512 synchronization feature (instead of AD9512 reset) · f1b0308f
  Jan Pospisil authored Aug 17, 2016
  
  f1b0308f
16 Aug, 2016 13 commits
- added OneWire function (not working yet); added calculation for pulse configuration · 548e07d3
  Jan Pospisil authored Aug 16, 2016
  
  548e07d3
- TODOs reorganized, added divider generics to OneWire module · 811d92b0
  Jan Pospisil authored Aug 16, 2016
  
  811d92b0
- magical 8 found? · b5dfdd72
  Jan Pospisil authored Aug 16, 2016
  
  b5dfdd72
- added edge detector for trigger input · f34f48b6
  Jan Pospisil authored Aug 16, 2016
  
  f34f48b6
- added readme.txt · a123e07c
  Jan Pospisil authored Aug 16, 2016
  
  a123e07c
- added possibility to write less data to the memories (for shorter SV simulation) · abaf1726
  Jan Pospisil authored Aug 16, 2016
  
  abaf1726
- fixed multi read/write SV reporting issues when accessing slice of the memory · cd3093e2
  Jan Pospisil authored Aug 16, 2016
  
  cd3093e2
- fixed ONE-SHOT issue (when overflow < trigger periodicity) · 8e25fb8d
  Jan Pospisil authored Aug 16, 2016
  
  8e25fb8d
- improved status reporting, added debug register · dbefc491
  Jan Pospisil authored Aug 16, 2016
  
  dbefc491
- fixed WB register "trigger latency" handling · f66860fa
  Jan Pospisil authored Aug 16, 2016
  
  f66860fa
- added debug register; added FSM state to debug register · 9fa27f2e
  Jan Pospisil authored Aug 16, 2016
  
  9fa27f2e
- fixed integer division in DAC functions; added errors report in SV trace debug;… · 33254a7d
  Jan Pospisil authored Aug 16, 2016
```
fixed integer division in DAC functions; added errors report in SV trace debug; added Enable/Disable and Start/Stop functions
```
  33254a7d
- removed old code · 6778f778
  Jan Pospisil authored Aug 16, 2016
  
  6778f778
15 Aug, 2016 4 commits
- added SV debug trace also for MULTI read/write · 2a626e4d
  Jan Pospisil authored Aug 15, 2016
  
  2a626e4d
- added second FMC signals and missing signals to testbench; used debug trace in testbench · 2939b35b
  Jan Pospisil authored Aug 15, 2016
  
  2939b35b
- added debug trace for SV testbench; added WaitForNotBusy function · 6a247f09
  Jan Pospisil authored Aug 15, 2016
  
  6a247f09
- reorganized CDC around pulse generators · 75016619
  Jan Pospisil authored Aug 15, 2016
  
  75016619
12 Aug, 2016 3 commits
- merged CDC for both channels in one entity, common signals have single CDC;… · a44b9d65
  Jan Pospisil authored Aug 12, 2016
```
merged CDC for both channels in one entity, common signals have single CDC; changed LED blinking frequency 5 Hz -> 15 Hz
```
  a44b9d65
- improved timing · 1da240df
  Jan Pospisil authored Aug 12, 2016
  
  1da240df
- improved clock frequencies parametrization; improved reset performance · be85196c
  Jan Pospisil authored Aug 12, 2016
  
  be85196c
11 Aug, 2016 7 commits
- added code for second FMC module · b7248beb
  Jan Pospisil authored Aug 11, 2016
  
  b7248beb
- updated uvm_agents submodule · 45178acf
  Jan Pospisil authored Aug 11, 2016
  
  45178acf
- improved timing by IOB registers packing for serial stream outputs · 7f6d4fd3
  Jan Pospisil authored Aug 11, 2016
  
  7f6d4fd3
- modified RF clock timing constraint according to Xilinx recommendation · 17c67fed
  Jan Pospisil authored Aug 11, 2016
  
  17c67fed
- changed LED "CLK IN" meaning; typo · 380842ae
  Jan Pospisil authored Aug 11, 2016
  
  380842ae
- modified SlowToggle to blink synchronously (with the same phase/polarity) on all outputs · a64076d8
  Jan Pospisil authored Aug 11, 2016
  
  a64076d8
- added fine delay control; added possibility to generate just set/reset pulse · 66eb9d1f
  Jan Pospisil authored Aug 11, 2016
  
  66eb9d1f
10 Aug, 2016 5 commits
- added time constraint for RF clock + modified design to meet this timing · 52532479
  Jan Pospisil authored Aug 10, 2016
  
  52532479
- slight improvement to SW driver · 4c8365c3
  Jan Pospisil authored Aug 10, 2016
  
  4c8365c3
- improved SVEC testbench - added pulse generating test · 95c418f9
  Jan Pospisil authored Aug 10, 2016
  
  95c418f9
- removed 'LED for "CLK IN"' TODO (already implemented); small changes and notes · 8d3f7250
  Jan Pospisil authored Aug 10, 2016
  
  8d3f7250
- more drivers! · 1b5b9eba
  Jan Pospisil authored Aug 10, 2016
  
  1b5b9eba
09 Aug, 2016 5 commits
- Merge branch 'master' of ohwr.org:fmc-projects/fmc-del-1ns-2cha · 70e70089
  Jan Pospisil authored Aug 09, 2016
  
  70e70089
- added test driver · 135ea1cb
  Jan Pospisil authored Aug 09, 2016
  
  135ea1cb
- improved SVEC testbench - added SPI test · 6cdd63cc
  Jan Pospisil authored Aug 09, 2016
  
  6cdd63cc
- improved SVEC testbench - added SPI test · dcc451fc
  Jan Pospisil authored Aug 09, 2016
  
  dcc451fc
- added AD9512 FUNC control; added FPGA LOOP clock output; fixed AD9512 SPI… · 7be9b719
  Jan Pospisil authored Aug 09, 2016
```
added AD9512 FUNC control; added FPGA LOOP clock output; fixed AD9512 SPI interface; improved front panel LEDs functionality; added AD9512 reset/sync.
```
  7be9b719