added test driver

135ea1cb · Jan Pospisil · 6cdd63cc · 135ea1cb
Commit 135ea1cb authored Aug 09, 2016 by Jan Pospisil
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FFPG_driver.py sw/FFPG_driver.py +108 -0

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--- a/sw/FFPG_driver.py
+++ b/sw/FFPG_driver.py
+#!/usr/bin/env python
+
+import sys
+sys.path.append('/usr/local/encore')
+import encoreio
+
+m = encoreio.Module.get_instance('fmc_fpg', 0)
+
+def WbRead(register):
+    return m.read(register)[0]
+
+def WbWrite(register, data):
+    m.write(register, (data,))
+
+def SpiRead(register):
+    WbWrite('spi_ss', 1)
+    WbWrite('spi_divider', 2)
+    WbWrite('spi_ctrl', 0x2618)
+    inst = 0x800000 | ((register & 0xff) << 8)
+    WbWrite('spi_tx_rx_0', inst)
+    WbWrite('spi_ctrl', 0x2718)
+    return WbRead('spi_tx_rx_0')
+
+def SpiWrite(register, data):
+    WbWrite('spi_ss', 1)
+    WbWrite('spi_divider', 2)
+    WbWrite('spi_ctrl', 0x2618)
+    inst = 0x000000 | ((register & 0xff) << 8) | (data & 0xff)
+    WbWrite('spi_tx_rx_0', inst)
+    WbWrite('spi_ctrl', 0x2718)
+
+def Ad9512Init():
+    # power down unused output (OUT2)
+    SpiWrite(0x3f, 0x03)
+    # select CLK1 input, power down CLK2 input
+    SpiWrite(0x45, 0x05)
+    # output frequency 200 MHz (divide by 2)
+    SpiWrite(0x4a, 0x00) # OUT0
+    SpiWrite(0x4c, 0x00) # OUT1
+    SpiWrite(0x4e, 0x00) # OUT2
+    SpiWrite(0x50, 0x00) # OUT3
+    SpiWrite(0x52, 0x00) # OUT4
+    # phase 0
+    SpiWrite(0x4b, 0x00) # OUT0
+    SpiWrite(0x4d, 0x00) # OUT1
+    SpiWrite(0x4f, 0x00) # OUT2
+    SpiWrite(0x51, 0x00) # OUT3
+    SpiWrite(0x53, 0x00) # OUT4
+    # function pin as sync
+    SpiWrite(0x58, 0x20)
+    # confirm write
+    SpiWrite(0x5a, 1)
+
+def WbSetBits(register, mask, bits):
+    value = WbRead(register)
+    value &= (~mask)
+    value |= (bits & mask)
+    WbWrite(register, value)
+    
+# 0 - front panel clock
+# 1 - FPGA loop clock
+# 2 - oscilator
+def SelectClock(clock):
+    if clock == 0:
+        # select CLK1 input, power down CLK2 input (AD9512)
+        SpiWrite(0x45, 0x05)
+        # confirm write
+        SpiWrite(0x5a, 1)
+    elif clock == 1:
+        # select CLK2 input, power down CLK1 input (AD9512)
+        SpiWrite(0x45, 0x02)
+        # confirm write
+        SpiWrite(0x5a, 1)
+        # select IN0 (SY58017)
+        WbSetBits('control', 3, 1)
+    elif clock == 2:
+        # select CLK2 input, power down CLK1 input (AD9512)
+        SpiWrite(0x45, 0x02)
+        # confirm write
+        SpiWrite(0x5a, 1)
+        # select IN1 (SY58017)
+        WbSetBits('control', 3, 0)
+    else:
+        raise Exception("Unknown clock!")
+
+# voltage in [V]
+def SetTriggerThreshold(voltage):
+    vdd = 5
+    bits = 16
+    code = int((voltage/vdd) * (2**bits))
+    code &= (2**bits)-1
+    WbWrite('trig_threshold', code)
+
+# compensation <-1;1)
+def SetVcxoFrequency(compensation):
+    vdd = 3.3
+    bits = 16
+    voltage = vdd * (compensation + 1) / 2
+    code = int((voltage/vdd) * (2**bits))
+    code &= (2**bits)-1
+    WbWrite('vcxo_voltage', code)
+
+# print(hex(SpiRead(0x4c)))
+
+Ad9512Init()
+SetTriggerThreshold(0.5)
+SelectClock(0)
+SetVcxoFrequency(0.99999)
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