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FMC DEL 1ns 2cha
Commit 6cdd63cc authored by Jan Pospisil's avatar Jan Pospisil
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improved SVEC testbench - added SPI test

parent 7be9b719
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Showing with 98 additions and 93 deletions
hdl/svec/sim/testbench/ConfigSvec.svh 0 → 100644
View file @ 6cdd63cc
`ifndef CONFIG_SVEC_SVH
`define CONFIG_SVEC_SVH
`define WB_SVEC_VME_ADDRESS 0
`define WB_FFPG_BASE (`WB_SVEC_VME_ADDRESS + 'h2_0000)
`define WB_FFPG_SPI_BASE (`WB_FFPG_BASE + 'h1000)
`define WB_FFPG_OW_BASE (`WB_FFPG_BASE + 'h1100)
`define WB_FFPG_CSR_BASE (`WB_FFPG_BASE + 'h1_0000)
`define WB_FFPG_SPI_REG(REG_ADDRESS) (`WB_FFPG_SPI_BASE + REG_ADDRESS)
`define WB_FFPG_OW_REG(REG_ADDRESS) (`WB_FFPG_OW_BASE + REG_ADDRESS)
`define WB_FFPG_CSR_REG(REG_ADDRESS) (`WB_FFPG_CSR_BASE + REG_ADDRESS)
// SPI regs.
`define SPI_TX_RX_0 'h00
`define SPI_TX_RX_1 'h04
`define SPI_TX_RX_2 'h08
`define SPI_TX_RX_3 'h0c
`define SPI_CTRL 'h10
`define SPI_DIVIDER 'h14
`define SPI_SS 'h18
`endif //CONFIG_SVEC_SVH
hdl/svec/sim/testbench/Testbench.sv
View file @ 6cdd63cc
......@@ -3,6 +3,7 @@
`include "fmc.svh"
`include "../../../ffpg/sim/testbench/ffpg_csr.svh"
`include "carrier_csr.svh"
`include "ConfigSvec.svh"
module Testbench;
......@@ -65,8 +66,6 @@ module Testbench;
assign Fmc0SpiAd9512Miso_i = 0;
task automatic init_vme64x_core(ref CBusAccessor_VME64x acc);
uint64_t rv;
/* map func0 to 0x80000000, A32 */
acc.write('h7ff63, 'h80, A32|CR_CSR|D08Byte3);
......@@ -78,137 +77,119 @@ module Testbench;
acc.set_default_modifiers(A32 | D32 | SINGLE);
endtask
initial begin
task automatic TestSdb(ref CBusAccessor_VME64x acc);
uint64_t d;
uint32_t wr_data;
uint64_t blt_addr[];
uint64_t blt_data[];
uint32_t base;
uint32_t address;
int i, result;
CBusAccessor_VME64x acc;
acc = new(VME);
#10us; // for PLL lock and reset settle
#20us;
init_vme64x_core(acc);
int i;
base = 'h0;
$display("Carrier SDB:\n");
base = `WB_SVEC_VME_ADDRESS;
$display("Carrier SDB:");
for (i=0; i<64; i = i+4) begin
address = base + i;
acc.read(address, d, A32|SINGLE|D32);
$display("[0x%x]: 0x%x\n", address, d[31:0]);
$display("[0x%x]: 0x%x", address, d[31:0]);
end
base = 'h2_0000 + 64*0;
$display("FFPG SDB:\n");
base = `WB_FFPG_BASE + 64*0;
$display("FFPG SDB:");
for (i=0; i<64; i = i+4) begin
address = base + i;
acc.read(address, d, A32|SINGLE|D32);
$display("[0x%x]: 0x%x\n", address, d[31:0]);
$display("[0x%x]: 0x%x", address, d[31:0]);
end
endtask
task automatic TestFfpgCsr(ref CBusAccessor_VME64x acc);
uint64_t d;
uint32_t base;
uint32_t address;
address = 'h2_0000 + 'h1_0000 + `ADDR_FFPG_STATUS;
$display("FFPG Status reg.:\n");
address = `WB_FFPG_CSR_REG(`ADDR_FFPG_STATUS);
$display("FFPG Status reg.:");
acc.read(address, d, A32|SINGLE|D32);
$display("[0x%x]: 0x%x\n", address, d[31:0]);
$display("[0x%x]: 0x%x", address, d[31:0]);
address = 'h2_0000 + 'h1_0000 + `ADDR_FFPG_CONTROL;
$display("Control reg. write:\n");
address = `WB_FFPG_CSR_REG(`ADDR_FFPG_CONTROL);
$display("Control reg. write:");
d = 4;
acc.write(address, d, A32|SINGLE|D32);
$display("[0x%x]: 0x%x\n", address, d[31:0]);
$display("[0x%x]: 0x%x", address, d[31:0]);
address = 'h2_0000 + 'h1_0000 + `ADDR_FFPG_STATUS;
$display("FFPG Status reg.:\n");
address = `WB_FFPG_CSR_REG(`ADDR_FFPG_STATUS);
$display("FFPG Status reg.:");
acc.read(address, d, A32|SINGLE|D32);
$display("[0x%x]: 0x%x\n", address, d[31:0]);
$display("[0x%x]: 0x%x", address, d[31:0]);
endtask
task automatic TestSpi(ref CBusAccessor_VME64x acc);
uint64_t d;
uint32_t base;
uint32_t address;
// $display("Release FMC0/1 reset\n");
// acc.write('h120C, 'h3, A32|SINGLE|D32);
address = `WB_FFPG_SPI_REG(`SPI_CTRL);
$display("Control reg. write:");
d = 'h2618; // ASS, NEG_TX/RX, LEN=24
acc.write(address, d, A32|SINGLE|D32);
$display("[0x%x]: 0x%x", address, d[31:0]);
address = `WB_FFPG_SPI_REG(`SPI_DIVIDER);
$display("Divider reg. write:");
d = 2; // f_SCLK ~ 20.833 MHz
acc.write(address, d, A32|SINGLE|D32);
$display("[0x%x]: 0x%x", address, d[31:0]);
// // Enable all interrupts
// $display("Enable FMC0 and FMC1 interrupt vectors\n");
// acc.write('h1308, 'h3, A32|SINGLE|D32);
// acc.read('h1310, d, A32|SINGLE|D32);
// $display("VIC interrupt mask = 0x%x\n",d);
// acc.write('h1300, 'h3, A32|SINGLE|D32);
address = `WB_FFPG_SPI_REG(`SPI_SS);
$display("SlaveSelect reg. write:");
d = 1;
acc.write(address, d, A32|SINGLE|D32);
$display("[0x%x]: 0x%x", address, d[31:0]);
// $display("Enable TRIGGER and END_ACQ in FMC0/1 EIC\n");
// acc.write('h2000, 'h3, A32|SINGLE|D32);
// acc.write('h6000, 'h3, A32|SINGLE|D32);
address = `WB_FFPG_SPI_REG(`SPI_TX_RX_0);
$display("TX reg. write:");
d = 'h80A500; // READ register 0xA5
acc.write(address, d, A32|SINGLE|D32);
$display("[0x%x]: 0x%x", address, d[31:0]);
// // Trigger setup (sw trigger)
// $display("Trigger setup\n");
// acc.write('h5308, 'h8, A32|SINGLE|D32);
address = `WB_FFPG_SPI_REG(`SPI_CTRL);
$display("Control reg. write:");
d = 'h2718; // ASS, NEG_TX/RX, LEN=24 + GO
acc.write(address, d, A32|SINGLE|D32);
$display("[0x%x]: 0x%x", address, d[31:0]);
#2us;
// // Acquisition setup
// $display("Acquisition setup\n");
// acc.write('h5320, 'h1, A32|SINGLE|D32); // 1 pre-trigger samples
// acc.write('h5324, 'hA, A32|SINGLE|D32); // 10 post-trigger samples
// acc.write('h5314, 'h1, A32|SINGLE|D32); // 1 shot
endtask
// // Make sure no acquisition is running
// acc.write('h5300, 'h2, A32|SINGLE|D32); // Send STOP command
initial begin
uint64_t blt_addr[];
uint64_t blt_data[];
// // Start acquisition
// $display("Start acquisition\n");
// acc.write('h5300, 'h1, A32|SINGLE|D32); // Send START command
CBusAccessor_VME64x acc;
// // Sw trigger
// #1us
// $display("Software trigger\n");
// acc.write('h5310, 'hFF, A32|SINGLE|D32);
acc = new(VME);
// /*
// // Data "FIFO" test
// acc.write('h2200, 'h0, A32|SINGLE|D32);
// acc.read('h2200, d, A32|SINGLE|D32);
// $display("Read DDR_ADR: 0x%x\n", d);
#10us; // for PLL lock and reset settle
#20us;
init_vme64x_core(acc);
// TestSdb(acc);
// TestFfpgCsr(acc);
TestSpi(acc);
// $display("Write data to DDR in BLT\n");
// blt_addr = {'h3000};
// blt_data = {'h1, 'h2, 'h3, 'h4, 'h5, 'h6, 'h7, 'h8 ,'h9, 'hA};
// acc.writem(blt_addr, blt_data, A32|BLT|D32, result);
// acc.write('h2200, 'h0, A32|SINGLE|D32);
// acc.read('h2200, d, A32|SINGLE|D32);
// $display("Read DDR_ADR: 0x%x\n", d);
// $display("Read data from DDR in BLT");
// blt_data = {};
// acc.readm(blt_addr, blt_data, A32|BLT|D32, result);
// for(i=0; i<10; i++)
// begin
// $display("Data %d: 0x%x\n", i, blt_data[i]);
// end
// */
// acc.write('h2200, 'h0, A32|SINGLE|D32);
// for(i=0; i<5; i++) begin
// acc.read('h3000, d, A32|SINGLE|D32);
// $display("Read %d: 0x%x\n", i, d);
// end
// acc.write('h2200, 'h0, A32|SINGLE|D32);
// for(i=0; i<2; i++) begin
// wr_data = i;
// acc.write('h3000, wr_data, A32|SINGLE|D32);
// $display("Write %d: 0x%x\n", i, wr_data);
// end
// acc.write('h2200, 'h0, A32|SINGLE|D32);
// for(i=0; i<5; i++) begin
// acc.read('h3000, d, A32|SINGLE|D32);
// $display("Read %d: 0x%x\n", i, d);
// for(i=0; i<10; i++) begin
// $display("Data %d: 0x%x\n", i, blt_data[i]);
// end
$stop;
......
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