Commit 380842ae authored by Jan Pospisil's avatar Jan Pospisil

changed LED "CLK IN" meaning; typo

parent a64076d8
......@@ -54,8 +54,6 @@ architecture syn of ClkRfDomain is
begin
-- Sv_Seed = 2491921240
-- for better timing
pInputReg: process(Clk_ik) is begin
if rising_edge(Clk_ik) then
......
......@@ -240,7 +240,7 @@ begin
LedSignal_b(3) <= TriggerRf;
-- CLK IN
LedSignal_b(4) <= ClkRf_k;
LedSignal_b(4) <= '1'; -- works just as "ON" LED as presence of ClkRf_ik cannot be sensed
cSlowToggle: entity work.SlowToggle(behavioral)
generic map (
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment