Skip to content

F
FMC DEL 1ns 2cha
Commit 52532479 authored by Jan Pospisil's avatar Jan Pospisil
Browse files
Options

added time constraint for RF clock + modified design to meet this timing

parent 4c8365c3
Hide whitespace changes
Inline Side-by-side
Showing with 34 additions and 8 deletions
hdl/ffpg/rtl/DelayedPulseGenerator/ClkRfDomain.vhd
View file @ 52532479
......@@ -56,8 +56,13 @@ begin
-- Sv_Seed = 2491921240
LastStreamPosition <= Overflow_ib16 - 1;
TriggerLatencyPlusOne <= TriggerLatency_ib16 + 1;
-- for better timing
pInputReg: process(Clk_ik) is begin
if rising_edge(Clk_ik) then
LastStreamPosition <= Overflow_ib16 - 1;
TriggerLatencyPlusOne <= TriggerLatency_ib16 + 1;
end if;
end process;
cFsm: entity work.Fsm(syn)
port map (
......@@ -72,9 +77,17 @@ begin
OutputEnable_o => OutputEnable
);
AddressEnableCounterReset <=
'1' when StreamPosition = (LastStreamPosition - c_MemLatency) else
Reset_ir;
-- for better timing
pAddressEnableCounterReset: process(Clk_ik) is begin
if rising_edge(Clk_ik) then
if StreamPosition = (LastStreamPosition - c_MemLatency) - 1 then
AddressEnableCounterReset <= '1';
else
AddressEnableCounterReset <= '0';
end if;
end if;
end process;
AddressEnableCounterSetValue <= TriggerLatencyPlusOne + c_MemLatency;
cAddressEnableCounter: entity work.Counter(syn)
generic map (
......@@ -114,9 +127,17 @@ begin
SetMemReadStrobe_o <= '0'; -- this is not connected anywhere!!
ResMemReadStrobe_o <= '0'; -- this is not connected anywhere!!
StreamReset <=
'1' when StreamPosition = LastStreamPosition else
'0';
-- for better timing
pStreamResetReg: process(Clk_ik) is begin
if rising_edge(Clk_ik) then
if StreamPosition = Overflow_ib16 - 2 then
StreamReset <= '1';
else
StreamReset <= '0';
end if;
end if;
end process;
StreamResetOrReset <= StreamReset or Reset_ir;
cStreamCounter: entity work.Counter(syn)
......
hdl/svec/syn/SvecFfpg.ucf
View file @ 52532479
......@@ -658,6 +658,11 @@ NET "Fmc0SpiAd9512Cs_on" IOSTANDARD = "LVCMOS25";
NET "Clk20_ik" TNM_NET = Clk20_ik;
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "Clk20_ik" 50 ns HIGH 50%;
# RF clock
NET "Fmc0ClkIn0_k" TNM_NET = Fmc0ClkIn0_k;
TIMESPEC TS_Fmc0ClkIn0_k = PERIOD "Fmc0ClkIn0_k" 5 ns HIGH 50%;
#===============================================================================
# False Path
#===============================================================================
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment