Commits · 66eb9d1fb169407b8450f4d69f9d8f93fcca016b · Projects / FMC DEL 1ns 2cha

11 Aug, 2016 1 commit
- added fine delay control; added possibility to generate just set/reset pulse · 66eb9d1f
  Jan Pospisil authored Aug 11, 2016
  
  66eb9d1f
10 Aug, 2016 5 commits
- added time constraint for RF clock + modified design to meet this timing · 52532479
  Jan Pospisil authored Aug 10, 2016
  
  52532479
- slight improvement to SW driver · 4c8365c3
  Jan Pospisil authored Aug 10, 2016
  
  4c8365c3
- improved SVEC testbench - added pulse generating test · 95c418f9
  Jan Pospisil authored Aug 10, 2016
  
  95c418f9
- removed 'LED for "CLK IN"' TODO (already implemented); small changes and notes · 8d3f7250
  Jan Pospisil authored Aug 10, 2016
  
  8d3f7250
- more drivers! · 1b5b9eba
  Jan Pospisil authored Aug 10, 2016
  
  1b5b9eba
09 Aug, 2016 5 commits
- Merge branch 'master' of ohwr.org:fmc-projects/fmc-del-1ns-2cha · 70e70089
  Jan Pospisil authored Aug 09, 2016
  
  70e70089
- added test driver · 135ea1cb
  Jan Pospisil authored Aug 09, 2016
  
  135ea1cb
- improved SVEC testbench - added SPI test · 6cdd63cc
  Jan Pospisil authored Aug 09, 2016
  
  6cdd63cc
- improved SVEC testbench - added SPI test · dcc451fc
  Jan Pospisil authored Aug 09, 2016
  
  dcc451fc
- added AD9512 FUNC control; added FPGA LOOP clock output; fixed AD9512 SPI… · 7be9b719
  Jan Pospisil authored Aug 09, 2016
```
added AD9512 FUNC control; added FPGA LOOP clock output; fixed AD9512 SPI interface; improved front panel LEDs functionality; added AD9512 reset/sync.
```
  7be9b719
08 Aug, 2016 1 commit
- improved reporting · 0a21e090
  Jan Pospisil authored Aug 08, 2016
  
  0a21e090
05 Aug, 2016 5 commits
- fixed pulse generation timing; fixed pulse comparison in testbench · 0177e735
  Jan Pospisil authored Aug 05, 2016
  
  0177e735
- fixed UniversalScoreboard FIFO access issue · bc8406ae
  Jan Pospisil authored Aug 05, 2016
  
  bc8406ae
- make channel random in pulse generation tests · 47c50607
  Jan Pospisil authored Aug 05, 2016
  
  47c50607
- added scoreboard control for FMC pulse transactions · 587ad118
  Jan Pospisil authored Aug 05, 2016
  
  587ad118
- added random pulse generation test · 709a1cd9
  Jan Pospisil authored Aug 05, 2016
  
  709a1cd9
04 Aug, 2016 7 commits
- fixed (some) metadata at the beginning of the simulation · 7241b5e5
  Jan Pospisil authored Aug 04, 2016
  
  7241b5e5
- fixed timing issue in pulse generator · b0c9b185
  Jan Pospisil authored Aug 04, 2016
  
  b0c9b185
- fixed start-up issue in HeartBeat.vhd · a5678863
  Jan Pospisil authored Aug 04, 2016
  
  a5678863
- modified Counter.Overflow_o behaviour · 64047f39
  Jan Pospisil authored Aug 04, 2016
  
  64047f39
- disabled NumericStd and StdArith warnings in simulation for time 0 ns · c8bcee93
  Jan Pospisil authored Aug 04, 2016
  
  c8bcee93
- added pulse generator test; reorganized FMC input signals (clock, trigger)… · a0418960
  Jan Pospisil authored Aug 04, 2016
```
added pulse generator test; reorganized FMC input signals (clock, trigger) parameters; enhanced configuration assert check
```
  a0418960
- fixed BYTE/WORD addressing mismatch · 8c0a8286
  Jan Pospisil authored Aug 04, 2016
  
  8c0a8286
03 Aug, 2016 6 commits
- fixed addressing problem; fixed vendor/device ID · 32205e2e
  Jan Pospisil authored Aug 03, 2016
  
  32205e2e
- added scripts for post_* simulations · 59b3472c
  Jan Pospisil authored Aug 03, 2016
  
  59b3472c
- added simulation for SVEC · 41f6f13e
  Jan Pospisil authored Aug 03, 2016
  
  41f6f13e
- added few comments; typos · 69c58070
  Jan Pospisil authored Aug 03, 2016
  
  69c58070
- fixed addressing scheme; added IO test architecture for SVEC top level · 998a4db9
  Jan Pospisil authored Aug 03, 2016
  
  998a4db9
- fixed registers removal in optimization in Xilinx XST · 9dd55085
  Jan Pospisil authored Aug 03, 2016
  
  9dd55085
29 Jul, 2016 2 commits
- added "clock dividers synchronization" function to the specification · f1b64718
  Jan Pospisil authored Jul 29, 2016
  
  f1b64718
- added another test for pulse generation; fixed pulse generation timing issue · 02de6d0d
  Jan Pospisil authored Jul 29, 2016
  
  02de6d0d
28 Jul, 2016 6 commits
- HeartBeat as a separate entity, typos · fc8c5bdd
  Jan Pospisil authored Jul 28, 2016
  
  fc8c5bdd
- clock domain naming clean up · bd9e5c2b
  Jan Pospisil authored Jul 28, 2016
  
  bd9e5c2b
- added FMC LED control · 7224bfda
  Jan Pospisil authored Jul 28, 2016
  
  7224bfda
- clock frequency generics clean up · d5cf7971
  Jan Pospisil authored Jul 28, 2016
  
  d5cf7971
- vme64x-core submodule added · 9393a482
  Jan Pospisil authored Jul 28, 2016
  
  9393a482
- name style fix · a7ade948
  Jan Pospisil authored Jul 28, 2016
  
  a7ade948
27 Jul, 2016 2 commits
- added UCF constraint file - implementation flow works (result is not tested) · b008376f
  Jan Pospisil authored Jul 27, 2016
  
  b008376f
- added glue logic to the SVEC top level entity SvecTopFfpg.vhd (inspired by… · 1a629ebc
  Jan Pospisil authored Jul 27, 2016
```
added glue logic to the SVEC top level entity SvecTopFfpg.vhd (inspired by git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha/fmc-adc-100m14b4cha-gw.git)
```
  1a629ebc