fixed timing issue in pulse generator

b0c9b185 · Jan Pospisil · a5678863 · b0c9b185 · b0c9b185
Commit b0c9b185 authored Aug 04, 2016 by Jan Pospisil
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Showing with 70 additions and 41 deletions

ClkRfDomain.vhd hdl/ffpg/rtl/DelayedPulseGenerator/ClkRfDomain.vhd +68 -39

Fsm.vhd hdl/ffpg/rtl/DelayedPulseGenerator/Fsm.vhd +2 -2

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--- a/hdl/ffpg/rtl/DelayedPulseGenerator/ClkRfDomain.vhd
+++ b/hdl/ffpg/rtl/DelayedPulseGenerator/ClkRfDomain.vhd
@@ -30,17 +30,33 @@ end entity;

 architecture syn of ClkRfDomain is

-    signal StreamReset, StreamReset_d: std_logic;
-    signal StreamResetOrReset: std_logic;
-    signal OutputEnable: std_logic;
+    constant c_MemLatency: integer := 1;
+
+    signal LastStreamPosition: unsigned(Overflow_ib16'range);
+
    signal GenerationEnable: std_logic;
+    signal OutputEnable: std_logic;
+    
+    signal AddressEnableCounterReset, AddressEnableCounterOverflow: std_logic;
+    signal AddressEnableCounterSetValue: unsigned(TriggerLatency_ib16'range);
+    
+    signal AddressCounterReset: std_logic;
+    signal AddressCounterSetValue: unsigned(TriggerLatency_ib16'range);
+    signal AddressCounterValue: unsigned(SetMemAddress_ob11'range);
+    
+    signal StreamReset, StreamResetOrReset: std_logic;
    signal StreamPosition: unsigned(Overflow_ib16'range);
+
    signal BitCounterOverflow, LoadShiftRegister: std_logic;
-    signal MemAddress: unsigned(SetMemAddress_ob11'range);
+    
    signal SetStream, ResetStream: std_logic;

 begin

+    --  Sv_Seed = 2491921240
+    
+    LastStreamPosition <= Overflow_ib16 - 1;
+
    cFsm: entity work.Fsm(syn)
        port map (
            Clk_ik => Clk_ik,
@@ -50,73 +66,86 @@ begin
            Trigger_i => Trigger_i,
            StreamReset_i => StreamReset,
            Running_o => Running_o,
-            OutputEnable_o => OutputEnable,
-            GenerationEnable_o => GenerationEnable
+            GenerationEnable_o => GenerationEnable,
+            OutputEnable_o => OutputEnable
        );

-    cStreamCounter: entity work.Counter(syn)
+    AddressEnableCounterReset <=
+        '1' when StreamPosition = (LastStreamPosition - c_MemLatency) else
+        Reset_ir;
+    AddressEnableCounterSetValue <= TriggerLatency_ib16 + c_MemLatency;
+    cAddressEnableCounter: entity work.Counter(syn)
        generic map (
-            g_Width => Overflow_ib16'length
+            g_Width => 5
        )
        port map (
            Clk_ik => Clk_ik,
-            Reset_ir => StreamResetOrReset,
+            Reset_ir => AddressEnableCounterReset,
            Enable_i => GenerationEnable,
            Set_i => Trigger_i,
-            SetValue_ib => TriggerLatency_ib16,
+            SetValue_ib => AddressEnableCounterSetValue(4 downto 0),
+            Overflow_o => AddressEnableCounterOverflow,
+            Value_ob => open
+        );
+
+    AddressCounterReset <=
+        '1' when StreamPosition = (LastStreamPosition - c_MemLatency - 1) else
+        Reset_ir;
+    AddressCounterSetValue <= (TriggerLatency_ib16 + c_MemLatency + 1);
+    cAddressCounter: entity work.Counter(syn)
+        generic map (
+            g_Width => SetMemAddress_ob11'length
+        )
+        port map (
+            Clk_ik => Clk_ik,
+            Reset_ir => AddressCounterReset,
+            Enable_i => AddressEnableCounterOverflow,
+            Set_i => Trigger_i,
+            SetValue_ib => AddressCounterSetValue(15 downto 5),
            Overflow_o => open,
-            Value_ob => StreamPosition
+            Value_ob => AddressCounterValue
        );
    
+    SetMemAddress_ob11 <= AddressCounterValue;
+    ResMemAddress_ob11 <= AddressCounterValue;
+    
+    SetMemReadStrobe_o <= AddressEnableCounterOverflow or AddressEnableCounterReset;
+    ResMemReadStrobe_o <= AddressEnableCounterOverflow or AddressEnableCounterReset;
+    
    StreamReset <=
-        '1' when StreamPosition = Overflow_ib16-1 else
+        '1' when StreamPosition = LastStreamPosition else
        '0';
    StreamResetOrReset <= StreamReset or Reset_ir;

-    cBitCounter: entity work.Counter(syn)
+    cStreamCounter: entity work.Counter(syn)
        generic map (
-            g_Width => 5
+            g_Width => Overflow_ib16'length
        )
        port map (
            Clk_ik => Clk_ik,
            Reset_ir => StreamResetOrReset,
            Enable_i => GenerationEnable,
            Set_i => Trigger_i,
-            SetValue_ib => TriggerLatency_ib16(4 downto 0),
-            Overflow_o => BitCounterOverflow,
-            Value_ob => open
-        );
-    
-    cStreamResetReg: entity work.Reg(syn)
-        port map (
-            Clk_ik => Clk_ik,
-            Reset_ir => Reset_ir,
-            Data_ib(0) => StreamReset,
-            Enable_i => '1',
-            Data_ob(0) => StreamReset_d
+            SetValue_ib => TriggerLatency_ib16,
+            Overflow_o => open,
+            Value_ob => StreamPosition
        );
    
-    LoadShiftRegister <= BitCounterOverflow or StreamReset_d;
-    
-    SetMemReadStrobe_o <= LoadShiftRegister;
-    ResMemReadStrobe_o <= LoadShiftRegister;
-    
-    cAddressCounter: entity work.Counter(syn)
+    cBitCounter: entity work.Counter(syn)
        generic map (
-            g_Width => SetMemAddress_ob11'length
+            g_Width => 5
        )
        port map (
            Clk_ik => Clk_ik,
            Reset_ir => StreamResetOrReset,
-            Enable_i => LoadShiftRegister,
+            Enable_i => GenerationEnable,
            Set_i => Trigger_i,
-            SetValue_ib => TriggerLatency_ib16(15 downto 5),
-            Overflow_o => open,
-            Value_ob => MemAddress
+            SetValue_ib => TriggerLatency_ib16(4 downto 0),
+            Overflow_o => BitCounterOverflow,
+            Value_ob => open
        );
    
-    SetMemAddress_ob11 <= MemAddress;
-    ResMemAddress_ob11 <= MemAddress;
+    LoadShiftRegister <= BitCounterOverflow or StreamReset;
    
    cShiftRegisterSet: entity work.ShiftRegister(right)
        generic map (

--- a/hdl/ffpg/rtl/DelayedPulseGenerator/Fsm.vhd
+++ b/hdl/ffpg/rtl/DelayedPulseGenerator/Fsm.vhd
@@ -16,8 +16,8 @@ entity Fsm is
        StreamReset_i: in std_logic;
        -- outputs
        Running_o: out std_logic := '0';
-        OutputEnable_o: out std_logic := '0';
-        GenerationEnable_o: out std_logic := '0'
+        GenerationEnable_o: out std_logic := '0';
+        OutputEnable_o: out std_logic := '0'
    );
 end entity;