clock frequency generics clean up

d5cf7971 · Jan Pospisil · 9393a482 · d5cf7971 · d5cf7971 · d5cf7971
Commit d5cf7971 authored Jul 28, 2016 by Jan Pospisil
8 changed files
--- a/hdl/ffpg/rtl/DacsController.vhd
+++ b/hdl/ffpg/rtl/DacsController.vhd
@@ -6,7 +6,7 @@ use work.FfpgPkg.all;

 entity DacsController is
    generic (
-        g_ClkFrequency: natural -- input clock frequency in MHz
+        g_ClkFrequency: positive -- input clock frequency in Hz
    );
    port (
        Clk_ik: in std_logic;
@@ -36,7 +36,7 @@ architecture syn of DacsController is
 		return Result;
 	end function;

-    function calculateSclkDivsel (ClkFrequency, DacFrequencyMax: natural) return std_logic_vector is
+    function f_calculateSclkDivsel(ClkFrequency, DacFrequencyMax: positive) return std_logic_vector is
        variable Result: integer;
    begin
        Result := log2(ClkFrequency/DacFrequencyMax);
@@ -51,8 +51,8 @@ architecture syn of DacsController is
        return std_logic_vector(to_unsigned(Result, 3));
    end function;

-    constant c_DacFrequencyMax: natural := 20; -- in MHz
-    constant c_SclkDivsel: std_logic_vector(2 downto 0) := calculateSclkDivsel(g_ClkFrequency, c_DacFrequencyMax);
+    constant c_DacFrequencyMax: positive := 20_000_000; -- in Hz
+    constant c_SclkDivsel: std_logic_vector(2 downto 0) := f_calculateSclkDivsel(g_ClkFrequency, c_DacFrequencyMax);

    signal Reset_nr: std_logic;
    signal TriggerDacEn, VcxoDacEn: std_logic;

--- a/hdl/ffpg/rtl/DelayController.vhd
+++ b/hdl/ffpg/rtl/DelayController.vhd
@@ -4,7 +4,7 @@ use ieee.numeric_std.all;

 entity DelayController is
    generic (
-        g_ClkFrequency: real -- input clock frequency in Hz
+        g_ClkFrequency: positive -- input clock frequency in Hz
    );
    port (
        Clk_ik: in std_logic;

--- a/hdl/ffpg/rtl/FfpgCore.vhd
+++ b/hdl/ffpg/rtl/FfpgCore.vhd
@@ -15,7 +15,7 @@ use work.wishbone_pkg.all;

 entity FfpgCore is
    generic (
-        g_ClkFrequency: natural -- input clock frequency in MHz
+        g_ClkFrequency: positive -- input clock frequency in Hz
    );
    port (
        -- Wishbone connection

--- a/hdl/ffpg/rtl/FfpgSlave.vhd
+++ b/hdl/ffpg/rtl/FfpgSlave.vhd
@@ -8,7 +8,7 @@ use work.wishbone_pkg.all;

 entity FfpgSlave is
    generic (
-        g_ClkFrequency: natural -- input clock frequency in MHz
+        g_ClkFrequency: positive -- input clock frequency in Hz
    );
    port (
        -- Wishbone connection
@@ -115,7 +115,7 @@ begin
    ----------------------------------
    cDelayController: entity work.DelayController(syn)
        generic map (
-            g_ClkFrequency => real(g_ClkFrequency)*1.0e6
+            g_ClkFrequency => g_ClkFrequency
        )
        port map (
            Clk_ik => Clk_ik,

--- a/hdl/ffpg/rtl/pulseGeneratorTime.vhd
+++ b/hdl/ffpg/rtl/pulseGeneratorTime.vhd
@@ -4,7 +4,7 @@ use ieee.numeric_std.all;

 entity PulseGeneratorTime is
    generic (
-        g_ClkFrequency: real;             -- input clock frequency in Hz
+        g_ClkFrequency: positive;    -- input clock frequency in Hz
        g_PulseMinWidthInTime: time  -- minimal pulse width in [s]
    );
    port (
@@ -17,7 +17,7 @@ end entity;

 architecture syn of PulseGeneratorTime is

-    constant c_ClkPeriod: time := (1.0 sec)/g_ClkFrequency;
+    constant c_ClkPeriod: time := (1.0 sec)/real(g_ClkFrequency);

    function f_CalculatePulseClk (ClkPeriod, PulseMinWidthInTime: time) return integer is
        variable Result: integer;

--- a/hdl/ffpg/sim/testbench/Config.svh
+++ b/hdl/ffpg/sim/testbench/Config.svh
@@ -2,7 +2,7 @@
 `define CONFIG_SVH

 // in MHz
-`define CLK_FREQ 200
+`define CLK_FREQ 200_000_000

 `define WB_ADDRESS_WIDTH 32
 `define WB_DATA_WIDTH 32

--- a/hdl/ffpg/sim/testbench/Testbench.sv
+++ b/hdl/ffpg/sim/testbench/Testbench.sv
@@ -7,7 +7,7 @@ import TestbenchPackage::*;

 module Testbench;

-    parameter c_ClkPeriod = 1000/`CLK_FREQ;
+    parameter c_ClkPeriod = 1e9/`CLK_FREQ; // in [ns]
    
    bit Clk_k, Reset_r;


--- a/hdl/svec/rtl/SvecTopFfpg.vhd
+++ b/hdl/svec/rtl/SvecTopFfpg.vhd