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FMC DEL 1ns 2cha
Commit 8c0a8286 authored by Jan Pospisil's avatar Jan Pospisil
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fixed BYTE/WORD addressing mismatch

parent 32205e2e
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Showing with 35 additions and 23 deletions
hdl/ffpg/rtl/WbSlaveWrapper.vhd
View file @ 8c0a8286
......@@ -72,7 +72,7 @@ begin
port map (
rst_n_i => Reset_nr,
clk_sys_i => Clk_ik,
wb_adr_i => Wb_i.adr(13 downto 0),
wb_adr_i => Wb_i.adr(15 downto 2), -- CSR is 32-bit addressed, WB is byte addressed
wb_dat_i => Wb_i.dat,
wb_dat_o => Wb_o.dat,
wb_cyc_i => Wb_i.cyc,
......
hdl/ffpg/sim/testbench/Config.svh
View file @ 8c0a8286
......@@ -8,13 +8,13 @@
`define WB_DATA_WIDTH 32
`define WB_TAG_WIDTH 0
`define FFPG_BASE_ADDR ('h 20000)
`define FFPG_BASE_ADDR ('h1_0000)
// in bits
`define STREAM_SIZE 65536
`define STREAM_SIZE 65_536
`include "ffpg_csr.svh"
`define GET_WB_WORD_ADDR(WB_BYTE_ADDR) (`FFPG_BASE_ADDR + (WB_BYTE_ADDR/(`WB_DATA_WIDTH/8)))
`define GET_WB_FFPG_ADDR(REG_ADDRESS) (`FFPG_BASE_ADDR + REG_ADDRESS)
`endif //CONFIG_SVH
hdl/ffpg/sim/testbench/TestbenchPackage.sv
View file @ 8c0a8286
......@@ -107,8 +107,8 @@ package TestbenchPackage;
UniversalSubscriber #(.T(Ad5600Transaction)) TriggerDacSubscriber;
UniversalSubscriber #(.T(Ad5600Transaction)) VcxoDacSubscriber;
DacScoreboard #(.WbAddress(`GET_WB_WORD_ADDR(`ADDR_FFPG_TRIGGER_THRESHOLD))) TriggerDacScoreboard;
DacScoreboard #(.WbAddress(`GET_WB_WORD_ADDR(`ADDR_FFPG_VCXO_VOLTAGE))) VcxoDacScoreboard;
DacScoreboard #(.WbAddress(`GET_WB_FFPG_ADDR(`ADDR_FFPG_TRIGGER_THRESHOLD))) TriggerDacScoreboard;
DacScoreboard #(.WbAddress(`GET_WB_FFPG_ADDR(`ADDR_FFPG_VCXO_VOLTAGE))) VcxoDacScoreboard;
function new(string name, uvm_component parent);
super.new(name, parent);
......@@ -146,8 +146,8 @@ package TestbenchPackage;
TriggerDacSubscriber = UniversalSubscriber #(.T(Ad5600Transaction))::type_id::create("TriggerDacSubscriber", this);
VcxoDacSubscriber = UniversalSubscriber #(.T(Ad5600Transaction))::type_id::create("VcxoDacSubscriber", this);
TriggerDacScoreboard = DacScoreboard #(.WbAddress(`GET_WB_WORD_ADDR(`ADDR_FFPG_TRIGGER_THRESHOLD)))::type_id::create("TriggerDacScoreboard", this);
VcxoDacScoreboard = DacScoreboard #(.WbAddress(`GET_WB_WORD_ADDR(`ADDR_FFPG_VCXO_VOLTAGE)))::type_id::create("VcxoDacScoreboard", this);
TriggerDacScoreboard = DacScoreboard #(.WbAddress(`GET_WB_FFPG_ADDR(`ADDR_FFPG_TRIGGER_THRESHOLD)))::type_id::create("TriggerDacScoreboard", this);
VcxoDacScoreboard = DacScoreboard #(.WbAddress(`GET_WB_FFPG_ADDR(`ADDR_FFPG_VCXO_VOLTAGE)))::type_id::create("VcxoDacScoreboard", this);
endfunction
function void connect_phase(uvm_phase phase);
......@@ -224,7 +224,7 @@ package TestbenchPackage;
start_item(tx);
assert(tx.randomize());
tx.direction_e = WB_B3_DIR_READ;
tx.address = `GET_WB_WORD_ADDR(`ADDR_FFPG_STATUS);
tx.address = `GET_WB_FFPG_ADDR(`ADDR_FFPG_STATUS);
finish_item(tx);
if (tx.response_e == WB_B3_RESPONSE_ACK_OK && tx.data[WbStatusBit] == 0) begin
busy = 0;
......@@ -279,10 +279,10 @@ package TestbenchPackage;
int WbDelayAddress;
case(ActiveOutput)
CH1_SET: WbDelayAddress = `GET_WB_WORD_ADDR(`ADDR_FFPG_CH1_DELAY_SET);
CH1_RESET: WbDelayAddress = `GET_WB_WORD_ADDR(`ADDR_FFPG_CH1_DELAY_RESET);
CH2_SET: WbDelayAddress = `GET_WB_WORD_ADDR(`ADDR_FFPG_CH2_DELAY_SET);
CH2_RESET: WbDelayAddress = `GET_WB_WORD_ADDR(`ADDR_FFPG_CH2_DELAY_RESET);
CH1_SET: WbDelayAddress = `GET_WB_FFPG_ADDR(`ADDR_FFPG_CH1_DELAY_SET);
CH1_RESET: WbDelayAddress = `GET_WB_FFPG_ADDR(`ADDR_FFPG_CH1_DELAY_RESET);
CH2_SET: WbDelayAddress = `GET_WB_FFPG_ADDR(`ADDR_FFPG_CH2_DELAY_SET);
CH2_RESET: WbDelayAddress = `GET_WB_FFPG_ADDR(`ADDR_FFPG_CH2_DELAY_RESET);
endcase
repeat (RepeatCount) begin
......@@ -292,7 +292,7 @@ package TestbenchPackage;
start_item(tx);
assert(tx.randomize());
tx.direction_e = WB_B3_DIR_READ;
tx.address = `GET_WB_WORD_ADDR(`ADDR_FFPG_STATUS);
tx.address = `GET_WB_FFPG_ADDR(`ADDR_FFPG_STATUS);
finish_item(tx);
if (tx.response_e == WB_B3_RESPONSE_ACK_OK && tx.data[`FFPG_STATUS_DELAY_CONFIGURATION_BUSY_OFFSET] == 0) begin
busy = 0;
......@@ -358,8 +358,8 @@ package TestbenchPackage;
task body;
td_wb_tx tx;
int SetMemBaseAddress = (Channel == 1) ? `GET_WB_WORD_ADDR(`BASE_FFPG_CH1_SET_MEM) : `GET_WB_WORD_ADDR(`BASE_FFPG_CH2_SET_MEM);
int ResMemBaseAddress = (Channel == 1) ? `GET_WB_WORD_ADDR(`BASE_FFPG_CH1_RES_MEM) : `GET_WB_WORD_ADDR(`BASE_FFPG_CH2_RES_MEM);
int SetMemBaseAddress = (Channel == 1) ? `GET_WB_FFPG_ADDR(`BASE_FFPG_CH1_SET_MEM) : `GET_WB_FFPG_ADDR(`BASE_FFPG_CH2_SET_MEM);
int ResMemBaseAddress = (Channel == 1) ? `GET_WB_FFPG_ADDR(`BASE_FFPG_CH1_RES_MEM) : `GET_WB_FFPG_ADDR(`BASE_FFPG_CH2_RES_MEM);
int OverflowInWords = getOverflowInWords();
// configure overflow
......@@ -367,7 +367,7 @@ package TestbenchPackage;
start_item(tx);
assert(tx.randomize());
tx.direction_e = WB_B3_DIR_WRITE;
tx.address = `GET_WB_WORD_ADDR(`ADDR_FFPG_OVERFLOW);
tx.address = `GET_WB_FFPG_ADDR(`ADDR_FFPG_OVERFLOW);
tx.data = Overflow;
finish_item(tx);
assert(tx.response_e == WB_B3_RESPONSE_ACK_OK);
......@@ -377,7 +377,7 @@ package TestbenchPackage;
start_item(tx);
assert(tx.randomize());
tx.direction_e = WB_B3_DIR_WRITE;
tx.address = `GET_WB_WORD_ADDR(`ADDR_FFPG_TRIGGER_LATENCY);
tx.address = `GET_WB_FFPG_ADDR(`ADDR_FFPG_TRIGGER_LATENCY);
tx.data = TriggerLatency;
finish_item(tx);
assert(tx.response_e == WB_B3_RESPONSE_ACK_OK);
......@@ -435,7 +435,7 @@ package TestbenchPackage;
start_item(tx);
assert(tx.randomize());
tx.direction_e = WB_B3_DIR_WRITE;
tx.address = `GET_WB_WORD_ADDR(`ADDR_FFPG_CONTROL);
tx.address = `GET_WB_FFPG_ADDR(`ADDR_FFPG_CONTROL);
tx.data = 1 << Position;
finish_item(tx);
assert(tx.response_e == WB_B3_RESPONSE_ACK_OK);
......@@ -508,7 +508,7 @@ package TestbenchPackage;
// test trigger DAC
seq = SeqSetDac::type_id::create("seq");
seq.Chip = Env_h.TriggerDacChip;
seq.WbDacAddress = `GET_WB_WORD_ADDR(`ADDR_FFPG_TRIGGER_THRESHOLD);
seq.WbDacAddress = `GET_WB_FFPG_ADDR(`ADDR_FFPG_TRIGGER_THRESHOLD);
seq.WbStatusBit = `FFPG_STATUS_DAC_TRIGGER_BUSY_OFFSET;
assert(seq.randomize());
seq.start(Env_h.WbAgent.seqr);
......@@ -516,7 +516,7 @@ package TestbenchPackage;
// test VCXO DAC
seq = SeqSetDac::type_id::create("seq");
seq.Chip = Env_h.VcxoDacChip;
seq.WbDacAddress = `GET_WB_WORD_ADDR(`ADDR_FFPG_VCXO_VOLTAGE);
seq.WbDacAddress = `GET_WB_FFPG_ADDR(`ADDR_FFPG_VCXO_VOLTAGE);
seq.WbStatusBit = `FFPG_STATUS_DAC_VCXO_BUSY_OFFSET;
assert(seq.randomize());
seq.start(Env_h.WbAgent.seqr);
......
hdl/svec/sim/testbench/Testbench.sv
View file @ 8c0a8286
......@@ -119,6 +119,17 @@ module Testbench;
acc.read(address, d, A32|SINGLE|D32);
$display("[0x%x]: 0x%x\n", address, d[31:0]);
address = 'h2_0000 + 'h1_0000 + `ADDR_FFPG_CONTROL;
$display("Control reg. write:\n");
d = 4;
acc.write(address, d, A32|SINGLE|D32);
$display("[0x%x]: 0x%x\n", address, d[31:0]);
address = 'h2_0000 + 'h1_0000 + `ADDR_FFPG_STATUS;
$display("FFPG Status reg.:\n");
acc.read(address, d, A32|SINGLE|D32);
$display("[0x%x]: 0x%x\n", address, d[31:0]);
// $display("Release FMC0/1 reset\n");
// acc.write('h120C, 'h3, A32|SINGLE|D32);
......
hdl/svec/sim/testbench/sim
View file @ 8c0a8286
......@@ -5,9 +5,10 @@ vsim -voptargs=+acc work.Testbench
# add wave -group Interface -r sim:/Testbench/LocalInterface/*
add wave -group DUT sim:/Testbench/cDut/cSvecTopFfpg/*
add wave -group Xbar sim:/Testbench/cDut/cSvecTopFfpg/cWbSdbCrossbar/*
add wave -group {Xbar SVEC} sim:/Testbench/cDut/cSvecTopFfpg/cWbSdbCrossbar/*
add wave -group {Xbar FFPG} sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cWbSdbCrossbar/*
add wave -group WbSlave sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cWbSlaveWrapper/*
# add wave -group WbSlave -r sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cWbSlaveWrapper/*
# add wave -group DacsController sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDacsController/*
# add wave -group DelayController -r sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayController/*
#
......
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