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FMC DEL 1ns 2cha
Commit 59b3472c authored by Jan Pospisil's avatar Jan Pospisil
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added scripts for post_* simulations

parent 41f6f13e
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Showing with 20 additions and 3 deletions
hdl/svec/sim/testbench/post_map 0 → 100644
View file @ 59b3472c
vcom -2008 -reportprogress 300 -work work ../../syn/netgen/map/SvecTopFfpg_map.vhd
vsim -voptargs=+acc -t ps -sdfmax /Testbench/cDut=../../syn/netgen/map/SvecTopFfpg_map.sdf work.Testbench
restart -f
run -all
\ No newline at end of file
hdl/svec/sim/testbench/post_par 0 → 100644
View file @ 59b3472c
vcom -2008 -reportprogress 300 -work work ../../syn/netgen/par/SvecTopFfpg_timesim.vhd
vsim -voptargs=+acc -t ps -sdfmax /Testbench/cDut=../../syn/netgen/par/SvecTopFfpg_timesim.sdf work.Testbench
restart -f
run -all
\ No newline at end of file
hdl/svec/sim/testbench/post_syn 0 → 100644
View file @ 59b3472c
vcom -2008 -reportprogress 300 -work work ../../syn/netgen/synthesis/SvecTopFfpg_synthesis.vhd
do res
\ No newline at end of file
hdl/svec/sim/testbench/post_tra 0 → 100644
View file @ 59b3472c
vcom -2008 -reportprogress 300 -work work ../../syn/netgen/translate/SvecTopFfpg_translate.vhd
do res
\ No newline at end of file
hdl/svec/syn/SvecFfpg.xise
View file @ 59b3472c
......@@ -35,7 +35,7 @@
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -133,6 +133,7 @@
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -253,7 +254,7 @@
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="SvecTopFfpg" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="SvecTopFfpgWrapper" xil_pn:valueState="non-default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -672,7 +673,9 @@
</file>
</files>
<bindings/>
<bindings>
<binding xil_pn:location="/SvecTopFfpg" xil_pn:name="SvecFfpg.ucf"/>
</bindings>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
......
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