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FMC DEL 1ns 2cha
Commit bd9e5c2b authored by Jan Pospisil's avatar Jan Pospisil
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clock domain naming clean up

parent 7224bfda
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Showing with 78 additions and 77 deletions
hdl/ffpg/rtl/DelayedPulseGenerator/RfClkDomain.vhd → hdl/ffpg/rtl/DelayedPulseGenerator/ClkRfDomain.vhd
View file @ bd9e5c2b
......@@ -4,7 +4,7 @@ use ieee.numeric_std.all;
use work.FfpgPkg.all;
entity RfClkDomain is
entity ClkRfDomain is
port (
-- main signals
Clk_ik: in std_logic;
......@@ -28,7 +28,7 @@ entity RfClkDomain is
);
end entity;
architecture syn of RfClkDomain is
architecture syn of ClkRfDomain is
signal StreamReset: std_logic;
signal StreamResetOrReset: std_logic;
......
hdl/ffpg/rtl/DelayedPulseGenerator/DelayedPulseGenerator.vhd
View file @ bd9e5c2b
......@@ -25,8 +25,8 @@ entity DelayedPulseGenerator is
Mode_i: in t_Mode;
ModeLoad_i: in std_logic;
Running_o: out std_logic;
-- generation (FMC), synchronous to SerialClock_ik
SerialClock_ik: in std_logic;
-- generation (FMC), synchronous to ClkRf_ik
ClkRf_ik: in std_logic;
SetStream_o: out std_logic;
ResetStream_o: out std_logic
);
......@@ -34,29 +34,30 @@ end entity;
architecture syn of DelayedPulseGenerator is
signal Overflow_b_slv, SerialClockOverflow_b_slv: std_logic_vector(Overflow_ib16'range);
signal TriggerLatency_b_slv, SerialClockTriggerLatency_b_slv: std_logic_vector(TriggerLatency_ib16'range);
signal ModeIn_slv, ModeOut_slv: std_logic_vector(1 downto 0);
signal Overflow_b_slv, OverflowRf_b_slv: std_logic_vector(Overflow_ib16'range);
signal TriggerLatency_b_slv, TriggerLatencyRf_b_slv: std_logic_vector(TriggerLatency_ib16'range);
signal Mode_slv, ModeRf_slv: std_logic_vector(1 downto 0);
signal SerialClockReset_r: std_logic;
signal SerialClockTrigger: std_logic;
signal SerialClockRunning: std_logic;
signal SerialClockOverflow_b: unsigned(Overflow_ib16'range);
signal SerialClockTriggerLatency_b: unsigned(TriggerLatency_ib16'range);
signal SerialClockMode: t_Mode;
signal SerialClockModeLoad: std_logic;
-- ClkRf clock domain
signal ResetRf_r: std_logic;
signal TriggerRf: std_logic;
signal RunningRf: std_logic;
signal OverflowRf_b: unsigned(Overflow_ib16'range);
signal TriggerLatencyRf_b: unsigned(TriggerLatency_ib16'range);
signal ModeRf: t_Mode;
signal ModeLoadRf: std_logic;
begin
----------------------------------
-- CDC syncers to the SerialClock_ik clock domain
-- CDC syncers to the ClkRf_ik clock domain
----------------------------------
cResetSyncer: entity work.ResetSyncer(syn)
port map (
Clk_ik => SerialClock_ik,
Clk_ik => ClkRf_ik,
Reset_ira => Reset_ir,
Reset_or => SerialClockReset_r
Reset_or => ResetRf_r
);
cTriggerSyncer: entity work.Delay(syn)
......@@ -66,73 +67,73 @@ begin
g_AsyncRegUsed => "TRUE"
)
port map (
Clk_ik => SerialClock_ik,
Clk_ik => ClkRf_ik,
Data_ib(0) => Trigger_i,
Data_ob(0) => SerialClockTrigger
Data_ob(0) => TriggerRf
);
Overflow_b_slv <= std_logic_vector(Overflow_ib16);
cOverflowSyncer: entity work.RegSyncer(syn)
port map (
ClkIn_ik => Clk_ik,
ClkOut_ik => SerialClock_ik,
ClkOut_ik => ClkRf_ik,
Data_ib => Overflow_b_slv,
Load_i => OverflowLoad_i,
Data_ob => SerialClockOverflow_b_slv,
Data_ob => OverflowRf_b_slv,
Load_o => open
);
SerialClockOverflow_b <= unsigned(SerialClockOverflow_b_slv);
OverflowRf_b <= unsigned(OverflowRf_b_slv);
TriggerLatency_b_slv <= std_logic_vector(TriggerLatency_ib16);
cTriggerLatencySyncer: entity work.RegSyncer(syn)
port map (
ClkIn_ik => Clk_ik,
ClkOut_ik => SerialClock_ik,
ClkOut_ik => ClkRf_ik,
Data_ib => TriggerLatency_b_slv,
Load_i => TriggerLatencyLoad_i,
Data_ob => SerialClockTriggerLatency_b_slv,
Data_ob => TriggerLatencyRf_b_slv,
Load_o => open
);
SerialClockTriggerLatency_b <= unsigned(SerialClockTriggerLatency_b_slv);
TriggerLatencyRf_b <= unsigned(TriggerLatencyRf_b_slv);
ModeIn_slv <= f_ModeToSlv(Mode_i);
Mode_slv <= f_ModeToSlv(Mode_i);
cModeSyncer: entity work.RegSyncer(syn)
port map (
ClkIn_ik => Clk_ik,
ClkOut_ik => SerialClock_ik,
Data_ib => ModeIn_slv,
ClkOut_ik => ClkRf_ik,
Data_ib => Mode_slv,
Load_i => ModeLoad_i,
Data_ob => ModeOut_slv,
Load_o => SerialClockModeLoad
Data_ob => ModeRf_slv,
Load_o => ModeLoadRf
);
SerialClockMode <= f_SlvToMode(ModeOut_slv);
ModeRf <= f_SlvToMode(ModeRf_slv);
----------------------------------
-- main core in SerialClock_ik clock domain
-- main core in ClkRf_ik clock domain
----------------------------------
cRfClkDomain: entity work.RfClkDomain(syn)
cClkRfDomain: entity work.ClkRfDomain(syn)
port map (
Clk_ik => SerialClock_ik,
Reset_ir => SerialClockReset_r,
Overflow_ib16 => SerialClockOverflow_b,
TriggerLatency_ib16 => SerialClockTriggerLatency_b,
Mode_i => SerialClockMode,
ModeLoad_i => SerialClockModeLoad,
Clk_ik => ClkRf_ik,
Reset_ir => ResetRf_r,
Overflow_ib16 => OverflowRf_b,
TriggerLatency_ib16 => TriggerLatencyRf_b,
Mode_i => ModeRf,
ModeLoad_i => ModeLoadRf,
SetMemAddress_ob11 => SetMemAddress_ob11,
SetMemData_ib32 => SetMemData_ib32,
SetMemReadStrobe_o => SetMemReadStrobe_o,
ResMemAddress_ob11 => ResMemAddress_ob11,
ResMemData_ib32 => ResMemData_ib32,
ResMemReadStrobe_o => ResMemReadStrobe_o,
Running_o => SerialClockRunning,
Trigger_i => SerialClockTrigger,
Running_o => RunningRf,
Trigger_i => TriggerRf,
SetStream_o => SetStream_o,
ResetStream_o => ResetStream_o
);
----------------------------------
-- CDC syncer from the SerialClock_ik clock domain
-- CDC syncer from the ClkRf_ik clock domain
----------------------------------
cRunningSyncer: entity work.Delay(syn)
......@@ -143,7 +144,7 @@ begin
)
port map (
Clk_ik => Clk_ik,
Data_ib(0) => SerialClockRunning,
Data_ib(0) => RunningRf,
Data_ob(0) => Running_o
);
......
hdl/ffpg/rtl/FfpgSlave.vhd
View file @ bd9e5c2b
......@@ -44,8 +44,8 @@ end entity;
architecture syn of FfpgSlave is
signal SerialStreamClock: std_logic;
signal SerialClockTrigger: std_logic;
signal ClkRf_k: std_logic;
signal TriggerRf: std_logic;
signal Ch1SetMemAddress_b11: unsigned(10 downto 0);
signal Ch1SetMemData_b32: unsigned(31 downto 0);
......@@ -68,7 +68,7 @@ architecture syn of FfpgSlave is
begin
SerialStreamClock <= ClkIn0_ik;
ClkRf_k <= ClkIn0_ik;
----------------------------------
-- Wishbone slave
......@@ -79,7 +79,7 @@ begin
Reset_ir => Reset_ir,
Wb_i => Wb_i,
Wb_o => Wb_o,
SerialStreamClock_i => SerialStreamClock,
ClkRf_ik => ClkRf_k,
Ch1SetMemAddress_ib11 => Ch1SetMemAddress_b11,
Ch1SetMemData_ob32 => Ch1SetMemData_b32,
Ch1SetMemReadStrobe_i => Ch1SetMemReadStrobe,
......@@ -171,7 +171,7 @@ begin
Mode_i => f_SlvToMode(WbRegsOutput.control_ch1_mode_o),
ModeLoad_i => WbRegsOutput.control_ch1_mode_load_o,
Running_o => WbRegsInput.status_channel_1_running_i,
SerialClock_ik => SerialStreamClock,
ClkRf_ik => ClkRf_k,
SetStream_o => Ch1Set,
ResetStream_o => Ch1Res_o
);
......@@ -195,7 +195,7 @@ begin
Mode_i => f_SlvToMode(WbRegsOutput.control_ch2_mode_o),
ModeLoad_i => WbRegsOutput.control_ch2_mode_load_o,
Running_o => WbRegsInput.status_channel_2_running_i,
SerialClock_ik => SerialStreamClock,
ClkRf_ik => ClkRf_k,
SetStream_o => Ch2Set,
ResetStream_o => Ch2Res_o
);
......@@ -219,9 +219,9 @@ begin
g_AsyncRegUsed => "TRUE"
)
port map (
Clk_ik => SerialStreamClock,
Clk_ik => ClkRf_k,
Data_ib(0) => Trigger_i,
Data_ob(0) => SerialClockTrigger
Data_ob(0) => TriggerRf
);
-- OUT1
......@@ -231,7 +231,7 @@ begin
LedSignal_b(2) <= Ch2Set;
-- TRIG IN
LedSignal_b(3) <= SerialClockTrigger;
LedSignal_b(3) <= TriggerRf;
-- CLK IN
LedSignal_b(4) <= '0';
......@@ -242,7 +242,7 @@ begin
g_Ticks => 5_000_000
)
port map (
Clk_ik => SerialStreamClock,
Clk_ik => ClkRf_k,
Reset_ir => '0',
Test_i => '0',
Signal_ib => LedSignal_b,
......
hdl/ffpg/rtl/WbSlaveWrapper.vhd
View file @ bd9e5c2b
......@@ -12,7 +12,7 @@ entity WbSlaveWrapper is
Reset_ir: in std_logic;
Wb_i: in t_wishbone_slave_in;
Wb_o: out t_wishbone_slave_out;
SerialStreamClock_i: in std_logic;
ClkRf_ik: in std_logic;
Ch1SetMemAddress_ib11: in unsigned(10 downto 0);
Ch1SetMemData_ob32: out unsigned(31 downto 0);
Ch1SetMemReadStrobe_i: in std_logic;
......@@ -81,7 +81,7 @@ begin
wb_we_i => Wb_i.we,
wb_ack_o => Wb_o.ack,
wb_stall_o => Wb_o.stall,
serial_stream_clk_ik => SerialStreamClock_i,
clk_rf_ik => ClkRf_ik,
ffpg_ch1_set_mem_addr_i => std_logic_vector(Ch1SetMemAddress_ib11),
unsigned(ffpg_ch1_set_mem_data_o) => Ch1SetMemData_ob32,
ffpg_ch1_set_mem_rd_i => Ch1SetMemReadStrobe_i,
......
hdl/ffpg/sim/testbench/make
View file @ bd9e5c2b
......@@ -49,7 +49,7 @@ vcom -2008 -reportprogress 300 -work work ../../rtl/WbSlaveWrapper.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/DelayController.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/DacsController.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/DelayedPulseGenerator/Fsm.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/DelayedPulseGenerator/RfClkDomain.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/DelayedPulseGenerator/ClkRfDomain.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/DelayedPulseGenerator/DelayedPulseGenerator.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/FfpgSlave.vhd
......
hdl/ffpg/wb_gen/ffpg_csr.wb
View file @ bd9e5c2b
......@@ -314,7 +314,7 @@ peripheral {
prefix = "ch1_set_mem";
width = 32;
size = 2048;
clock = "serial_stream_clk_ik";
clock = "clk_rf_ik";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -324,7 +324,7 @@ peripheral {
prefix = "ch1_res_mem";
width = 32;
size = 2048;
clock = "serial_stream_clk_ik";
clock = "clk_rf_ik";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -334,7 +334,7 @@ peripheral {
prefix = "ch2_set_mem";
width = 32;
size = 2048;
clock = "serial_stream_clk_ik";
clock = "clk_rf_ik";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -344,7 +344,7 @@ peripheral {
prefix = "ch2_res_mem";
width = 32;
size = 2048;
clock = "serial_stream_clk_ik";
clock = "clk_rf_ik";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......
hdl/svec/syn/SvecFfpg.xise
View file @ bd9e5c2b
......@@ -385,15 +385,15 @@
</file>
<file xil_pn:name="../../ffpg/rtl/FfpgSlave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
</file>
<file xil_pn:name="../../ffpg/rtl/DacsController.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
</file>
<file xil_pn:name="../../ffpg/rtl/DelayController.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
</file>
<file xil_pn:name="../../ffpg/rtl/WbSlaveWrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
......@@ -401,13 +401,13 @@
</file>
<file xil_pn:name="../../ffpg/rtl/DelayedPulseGenerator/DelayedPulseGenerator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
</file>
<file xil_pn:name="../../ffpg/rtl/DelayedPulseGenerator/Fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../ffpg/rtl/DelayedPulseGenerator/RfClkDomain.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ffpg/rtl/DelayedPulseGenerator/ClkRfDomain.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file>
......@@ -481,7 +481,7 @@
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
......@@ -493,7 +493,7 @@
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
......@@ -517,7 +517,7 @@
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/>
......@@ -549,11 +549,11 @@
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="60"/>
<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
<association xil_pn:name="Implementation" xil_pn:seqID="67"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME64xCore_Top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_bus.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
......@@ -613,11 +613,11 @@
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="76"/>
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="77"/>
<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="78"/>
......@@ -633,11 +633,11 @@
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
<association xil_pn:name="Implementation" xil_pn:seqID="67"/>
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="82"/>
<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="83"/>
......@@ -653,15 +653,15 @@
</file>
<file xil_pn:name="../rtl/carrier_csr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="86"/>
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
</file>
<file xil_pn:name="../../ffpg/rtl/SlowToggle.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="87"/>
<association xil_pn:name="Implementation" xil_pn:seqID="70"/>
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="88"/>
<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
<association xil_pn:name="Implementation" xil_pn:seqID="70"/>
</file>
<file xil_pn:name="SvecFfpg.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......
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