added "clock dividers synchronization" function to the specification

f1b64718 · Jan Pospisil · 02de6d0d · f1b64718 · f1b64718
Commit f1b64718 authored Jul 29, 2016 by Jan Pospisil
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Showing with 15 additions and 6 deletions

FFPG-module-specification.txt doc/FFPG-module-specification.txt +13 -6

FfpgCore.vhd hdl/ffpg/rtl/FfpgCore.vhd +2 -0

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--- a/doc/FFPG-module-specification.txt
+++ b/doc/FFPG-module-specification.txt
@@ -14,7 +14,6 @@ A) Controllable blocks and connections on the card
 	communications
 		SPI/QSPI/Microwire/DSP <- FMC ("SPI_VCXO", AD5660)
 		1bit <- FMC ("CLK2_SEL", SY58017U)
-		1bit <- FMC ("AD9152_FUNC", AD9512)
 		SPI/SSR <-> FMC ("SPI_AD9512", AD9512)

 2) channels configuration (2 times, MC100EP195B)
@@ -35,6 +34,9 @@ A) Controllable blocks and connections on the card
 7) LEDs
 	4bits <- FMC

+8) Clock synchronization
+    1bit <- FMC ("AD9152_FUNC", AD9512)
+
 X) Serial EEPROM (24AA64T)
 	I2C + address <-> FMC
 	(Handled by FMC carrier board)
@@ -115,8 +117,8 @@ B) Controlling module logic
  WB for read only. It will contain 9 bits map with the status of following components. An unset
  bit (i.e. log.0) means there is no work carried by the component at that time, thus the component
  is ready for an operation and it is accepting commands. A set bit (i.e. log.1) means that the
-  component is actually busy and doesn't accept any command. Exceptions are bits 4, 5, 7 and 8, which
-  (if set to log.1) doesn't prevent from issuing new commands.
+  component is actually busy and doesn't accept any command. Exceptions are bits 4, 5, 7 and 8,
+  which (if set to log.1) doesn't prevent from issuing new commands.
    0 - Clock infrastructure configuration
    1 - VCXO DAC AD5660
    2 - Clock selection
@@ -127,7 +129,7 @@ B) Controlling module logic
    7 - Generator running on CH1
    8 - Generator running on CH2

-8) The control register will hold all spare-bits configuration:
+8) The control register will hold all sparse-bits configuration:
    Clock selection (enum: external/loop/on-board)
    Output enable configuration (2 bits map)
    Mode selection (in control register - 2x enum: stop/continuous/one-shot)
@@ -138,8 +140,13 @@ B) Controlling module logic
    TRIG IN LED will blink when there will be any activity on trigger input
    CLK IN LED will be on when there will be any activity on CLK input

-8) Frequency of the clock to which serial streams will be synchronous can be retrieved by reading
+8) Frequency of the clock, to which serial streams will be synchronous, can be retrieved by reading
  one WB register.

-9) Others: FMC outputs CAL_OUT coming from channels will not be used. The loop clock from FPGA
+9) The clock dividers in AD9512 will be synchronized via AD9152_FUNC signal. The trigger input
+  signal will be used for this synchronization. Synchronization will be done on request via WB
+  register. Status of the last synchronization (success/failure) will be signalized by one bit in
+  the WB status register.
+ 
+X) Others: FMC outputs CAL_OUT coming from channels will not be used. The loop clock from FPGA
  coming to FMC card will carry WB clock used by the FPGA module.
\ No newline at end of file
--- a/hdl/ffpg/rtl/FfpgCore.vhd
+++ b/hdl/ffpg/rtl/FfpgCore.vhd
@@ -4,6 +4,8 @@
 --   ? clock divider
 --   - frequency sense
 --   - LED for "CLK IN"
+--   - timing
+--   - clock dividers synchronization

 library ieee;
 use ieee.std_logic_1164.all;