fixed start-up issue in HeartBeat.vhd

a5678863 · Jan Pospisil · 64047f39 · a5678863 · a5678863
Commit a5678863 authored Aug 04, 2016 by Jan Pospisil
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Showing with 19 additions and 5 deletions

HeartBeat.vhd hdl/svec/rtl/HeartBeat.vhd +7 -4

HeartBeat_tb.vhd hdl/svec/rtl/HeartBeat_tb.vhd +12 -1

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--- a/hdl/svec/rtl/HeartBeat.vhd
+++ b/hdl/svec/rtl/HeartBeat.vhd
@@ -128,10 +128,13 @@ begin
        if rising_edge(Clk_ik) then
            if Reset_ir = '1' then
                HeartBeat_o <= '0';
-            elsif PwmCounter_b = 0 then
-                HeartBeat_o <= '1';
-            elsif PwmCounter_b = PwmValue_bd then
-                HeartBeat_o <= '0';
+            else
+                if PwmCounter_b = 0 then
+                    HeartBeat_o <= '1';
+                end if;
+                if PwmCounter_b = PwmValue_bd then
+                    HeartBeat_o <= '0';
+                end if;
            end if;
        end if;
    end process;

--- a/hdl/svec/rtl/HeartBeat_tb.vhd
+++ b/hdl/svec/rtl/HeartBeat_tb.vhd
@@ -15,6 +15,7 @@ architecture testbench of HeartBeat_tb is
    end procedure;

    signal Clk_ik, Reset_ir, HeartBeat_o: std_logic;
+    signal HeartBeatPwmValue: time := 0 ns;

 begin

@@ -39,10 +40,20 @@ begin
        Reset_ir <= '1';
        f_Tick(5);
        Reset_ir <= '0';
-        f_Tick(10e3);
+        f_Tick(1e6);

        assert false report "NONE. End of simulation." severity failure;
        wait;
    end process pTest;
+    
+    pRC: process (HeartBeat_o) is
+        variable LastOn: time := 0 ns;
+    begin
+        if rising_edge(HeartBeat_o) then
+            LastOn := now;
+        else
+            HeartBeatPwmValue <= now - LastOn;
+        end if;
+    end process;

 end architecture;