Skip to content

F
FMC DEL 1ns 2cha
Commit c8bcee93 authored by Jan Pospisil's avatar Jan Pospisil
Browse files
Options

disabled NumericStd and StdArith warnings in simulation for time 0 ns

parent a0418960
Hide whitespace changes
Inline Side-by-side
Showing with 27 additions and 15 deletions
hdl/ffpg/sim/testbench/res
View file @ c8bcee93
# restart simulation with new random seed
restart -force -sv_seed random
run -all
\ No newline at end of file
do run
\ No newline at end of file
hdl/ffpg/sim/testbench/ress
View file @ c8bcee93
# restart simulation with the Same random seed
restart -force
run -all
\ No newline at end of file
do run
\ No newline at end of file
hdl/ffpg/sim/testbench/run 0 → 100644
View file @ c8bcee93
set NumericStdNoWarnings 1
set StdArithNoWarnings 1
run 0 ns
set NumericStdNoWarnings 0
set StdArithNoWarnings 0
run -all
\ No newline at end of file
hdl/ffpg/sim/testbench/sim
View file @ c8bcee93
......@@ -11,16 +11,20 @@ add wave -group DelayController -r sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDela
add wave -group DelayedPulseGeneratorCh1 sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh1/*
add wave -group DelayedPulseGeneratorCh1 -group ClkRfDomain sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh1/cClkRfDomain/*
add wave -group DelayedPulseGeneratorCh1 -group ClkRfDomain -group Fsm sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh1/cClkRfDomain/cFsm/*
add wave -group DelayedPulseGeneratorCh1 -group ClkRfDomain -group BitCounter sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh1/cClkRfDomain/cBitCounter/*
add wave -group DelayedPulseGeneratorCh1 -group ClkRfDomain -group AddressEnableCounter sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh1/cClkRfDomain/cAddressEnableCounter/*
add wave -group DelayedPulseGeneratorCh1 -group ClkRfDomain -group AddressCounter sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh1/cClkRfDomain/cAddressCounter/*
add wave -group DelayedPulseGeneratorCh1 -group ClkRfDomain -group StreamCounter sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh1/cClkRfDomain/cStreamCounter/*
add wave -group DelayedPulseGeneratorCh1 -group ClkRfDomain -group BitCounter sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh1/cClkRfDomain/cBitCounter/*
add wave -group DelayedPulseGeneratorCh1 -group ClkRfDomain -group ShiftRegisterSet sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh1/cClkRfDomain/cShiftRegisterSet/*
add wave -group DelayedPulseGeneratorCh1 -group ClkRfDomain -group ShiftRegisterReset sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh1/cClkRfDomain/cShiftRegisterReset/*
add wave -group DelayedPulseGeneratorCh2 sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh2/*
add wave -group DelayedPulseGeneratorCh2 -group ClkRfDomain sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh2/cClkRfDomain/*
add wave -group DelayedPulseGeneratorCh2 -group ClkRfDomain -group Fsm sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh2/cClkRfDomain/cFsm/*
add wave -group DelayedPulseGeneratorCh2 -group ClkRfDomain -group BitCounter sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh2/cClkRfDomain/cBitCounter/*
add wave -group DelayedPulseGeneratorCh2 -group ClkRfDomain -group AddressEnableCounter sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh2/cClkRfDomain/cAddressEnableCounter/*
add wave -group DelayedPulseGeneratorCh2 -group ClkRfDomain -group AddressCounter sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh2/cClkRfDomain/cAddressCounter/*
add wave -group DelayedPulseGeneratorCh2 -group ClkRfDomain -group StreamCounter sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh2/cClkRfDomain/cStreamCounter/*
add wave -group DelayedPulseGeneratorCh2 -group ClkRfDomain -group BitCounter sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh2/cClkRfDomain/cBitCounter/*
add wave -group DelayedPulseGeneratorCh2 -group ClkRfDomain -group ShiftRegisterSet sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh2/cClkRfDomain/cShiftRegisterSet/*
add wave -group DelayedPulseGeneratorCh2 -group ClkRfDomain -group ShiftRegisterReset sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh2/cClkRfDomain/cShiftRegisterReset/*
......@@ -29,5 +33,5 @@ configure wave -valuecolwidth 100
configure wave -signalnamewidth 1
sv_reseed random
run -all
do run
wave zoomfull
hdl/svec/sim/testbench/post_map
View file @ c8bcee93
vcom -2008 -reportprogress 300 -work work ../../syn/netgen/map/SvecTopFfpg_map.vhd
vsim -voptargs=+acc -t ps -sdfmax /Testbench/cDut=../../syn/netgen/map/SvecTopFfpg_map.sdf work.Testbench
restart -f
run -all
\ No newline at end of file
do res
\ No newline at end of file
hdl/svec/sim/testbench/post_par
View file @ c8bcee93
vcom -2008 -reportprogress 300 -work work ../../syn/netgen/par/SvecTopFfpg_timesim.vhd
vsim -voptargs=+acc -t ps -sdfmax /Testbench/cDut=../../syn/netgen/par/SvecTopFfpg_timesim.sdf work.Testbench
restart -f
run -all
\ No newline at end of file
do res
\ No newline at end of file
hdl/svec/sim/testbench/res
View file @ c8bcee93
# restart simulation with new random seed
restart -force -sv_seed random
run -all
\ No newline at end of file
do run
\ No newline at end of file
hdl/svec/sim/testbench/run 0 → 100644
View file @ c8bcee93
set NumericStdNoWarnings 1
set StdArithNoWarnings 1
run 0 ns
set NumericStdNoWarnings 0
set StdArithNoWarnings 0
run -all
\ No newline at end of file
hdl/svec/sim/testbench/sim
View file @ c8bcee93
......@@ -33,9 +33,5 @@ configure wave -valuecolwidth 100
configure wave -signalnamewidth 1
sv_reseed random
set NumericStdNoWarnings 1
set StdArithNoWarnings 1
run -all
# set NumericStdNoWarnings 0
# set StdArithNoWarnings 1
do run
wave zoomfull
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment