fixed registers removal in optimization in Xilinx XST

9dd55085 · Jan Pospisil · f1b64718 · 9dd55085
Commit 9dd55085 authored Aug 03, 2016 by Jan Pospisil
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Showing with 22 additions and 6 deletions

ResetSyncer.vhd hdl/ffpg/rtl/ResetSyncer.vhd +22 -6

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--- a/hdl/ffpg/rtl/ResetSyncer.vhd
+++ b/hdl/ffpg/rtl/ResetSyncer.vhd
@@ -24,23 +24,39 @@ architecture syn of ResetSyncer is
 	end function;

 	attribute ASYNC_REG: string;
-	
+    attribute KEEP:string;
+    attribute SHREG_EXTRACT: string;
+
 	constant c_Inversion: std_logic := if_sl(g_Inverted, '1', '0');

-	signal ShiftRegister: std_logic_vector(g_Length-1 downto 0) := (others => ('1' xor c_Inversion));
+	signal ShiftRegister0: std_logic := ('1' xor c_Inversion);
+	signal ShiftRegister1: std_logic := ('1' xor c_Inversion);
+	signal ShiftRegister2: std_logic := ('1' xor c_Inversion);

-	attribute ASYNC_REG of ShiftRegister: signal is "TRUE";
+	attribute ASYNC_REG of ShiftRegister0: signal is "true";
+	attribute ASYNC_REG of ShiftRegister1: signal is "true";
+	attribute ASYNC_REG of ShiftRegister2: signal is "true";
+    attribute KEEP of ShiftRegister0: signal is "true";
+    attribute KEEP of ShiftRegister1: signal is "true";
+    attribute KEEP of ShiftRegister2: signal is "true";
+    attribute SHREG_EXTRACT of ShiftRegister0: signal is "no";
+    attribute SHREG_EXTRACT of ShiftRegister1: signal is "no";
+    attribute SHREG_EXTRACT of ShiftRegister2: signal is "no";

 begin

 	pSyncer: process (Clk_ik, Reset_ira) begin
 		if Reset_ira = ('1' xor c_Inversion) then
-			ShiftRegister <= (others => ('1' xor c_Inversion));
+			ShiftRegister0 <= ('1' xor c_Inversion);
+			ShiftRegister1 <= ('1' xor c_Inversion);
+			ShiftRegister2 <= ('1' xor c_Inversion);
 		elsif rising_edge(Clk_ik) then
-			ShiftRegister <= ShiftRegister(g_Length-2 downto 0)&('0' xor c_Inversion);
+            ShiftRegister0 <= ('0' xor c_Inversion);
+            ShiftRegister1 <= ShiftRegister0;
+            ShiftRegister2 <= ShiftRegister1;
 		end if;
 	end process;
 	
-	Reset_or <= ShiftRegister(g_Length-1);
+	Reset_or <= ShiftRegister2;

 end architecture;