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FMC DEL 1ns 2cha
Commit 41f6f13e authored by Jan Pospisil's avatar Jan Pospisil
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added simulation for SVEC

parent 69c58070
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.gitignore
View file @ 41f6f13e
......@@ -2,16 +2,18 @@
/doc/manual/ffpg_csr.tex
/doc/manual/svec/carrier_csr.htm
/doc/manual/svec/carrier_csr.tex
/hdl/ffpg/wb_gen/*.h
/hdl/*/wb_gen/*.h
/hdl/*/sim/testbench/work/*
/hdl/*/sim/testbench/tr_db.log
/hdl/*/sim/testbench/transcript
/hdl/*/sim/testbench/uvm.log
/hdl/*/sim/testbench/vsim.wlf
/hdl/*/sim/testbench/wlf*
/hdl/*/sim/testbench/*.vstf
/hdl/ffpg/rtl/ffpg_csr.vhd
/hdl/ffpg/rtl/ffpg_csr_pkg.vhd
/hdl/ffpg/sim/testbench/work/*
/hdl/ffpg/sim/testbench/tr_db.log
/hdl/ffpg/sim/testbench/transcript
/hdl/ffpg/sim/testbench/uvm.log
/hdl/ffpg/sim/testbench/vsim.wlf
/hdl/ffpg/sim/testbench/wlf*
/hdl/ffpg/sim/testbench/*.vstf
/hdl/ffpg/sim/testbench/ffpg_csr.svh
/hdl/svec/syn
/hdl/svec/wb_gen/*.h
/hdl/svec/rtl/carrier_csr.vhd
/hdl/svec/sim/testbench/carrier_csr.svh
hdl/ffpg/sim/testbench/ffpg_csr.svh deleted 100644 → 0
View file @ 69c58070
`define ADDR_FFPG_STATUS 16'h0
`define FFPG_STATUS_CLOCK_INFRASTRUCTURE_BUSY_OFFSET 0
`define FFPG_STATUS_CLOCK_INFRASTRUCTURE_BUSY 32'h00000001
`define FFPG_STATUS_DAC_VCXO_BUSY_OFFSET 1
`define FFPG_STATUS_DAC_VCXO_BUSY 32'h00000002
`define FFPG_STATUS_DAC_TRIGGER_BUSY_OFFSET 2
`define FFPG_STATUS_DAC_TRIGGER_BUSY 32'h00000004
`define FFPG_STATUS_CLOCK_SELECTION_BUSY_OFFSET 3
`define FFPG_STATUS_CLOCK_SELECTION_BUSY 32'h00000008
`define FFPG_STATUS_DELAY_CONFIGURATION_BUSY_OFFSET 4
`define FFPG_STATUS_DELAY_CONFIGURATION_BUSY 32'h00000010
`define FFPG_STATUS_CHANNEL_1_OE_OFFSET 5
`define FFPG_STATUS_CHANNEL_1_OE 32'h00000020
`define FFPG_STATUS_CHANNEL_2_OE_OFFSET 6
`define FFPG_STATUS_CHANNEL_2_OE 32'h00000040
`define FFPG_STATUS_CHANNEL_1_RUNNING_OFFSET 7
`define FFPG_STATUS_CHANNEL_1_RUNNING 32'h00000080
`define FFPG_STATUS_CHANNEL_2_RUNNING_OFFSET 8
`define FFPG_STATUS_CHANNEL_2_RUNNING 32'h00000100
`define ADDR_FFPG_CONTROL 16'h4
`define FFPG_CONTROL_CLOCK_SELECTION_OFFSET 0
`define FFPG_CONTROL_CLOCK_SELECTION 32'h00000003
`define FFPG_CONTROL_CH1_OE_OFFSET 2
`define FFPG_CONTROL_CH1_OE 32'h00000004
`define FFPG_CONTROL_CH2_OE_OFFSET 3
`define FFPG_CONTROL_CH2_OE 32'h00000008
`define FFPG_CONTROL_CH1_MODE_OFFSET 4
`define FFPG_CONTROL_CH1_MODE 32'h00000030
`define FFPG_CONTROL_CH2_MODE_OFFSET 6
`define FFPG_CONTROL_CH2_MODE 32'h000000c0
`define ADDR_FFPG_VCXO_VOLTAGE 16'h8
`define ADDR_FFPG_CLOCK_DIVIDER 16'hc
`define FFPG_CLOCK_DIVIDER_LO_OFFSET 0
`define FFPG_CLOCK_DIVIDER_LO 32'h0000000f
`define FFPG_CLOCK_DIVIDER_HI_OFFSET 4
`define FFPG_CLOCK_DIVIDER_HI 32'h000000f0
`define ADDR_FFPG_CH1_DELAY_SET 16'h10
`define ADDR_FFPG_CH1_DELAY_RESET 16'h14
`define ADDR_FFPG_CH2_DELAY_SET 16'h18
`define ADDR_FFPG_CH2_DELAY_RESET 16'h1c
`define ADDR_FFPG_TRIGGER_THRESHOLD 16'h20
`define ADDR_FFPG_OVERFLOW 16'h24
`define ADDR_FFPG_TRIGGER_LATENCY 16'h28
`define ADDR_FFPG_FREQUENCY 16'h2c
`define BASE_FFPG_CH1_SET_MEM 16'h2000
`define SIZE_FFPG_CH1_SET_MEM 32'h800
`define BASE_FFPG_CH1_RES_MEM 16'h4000
`define SIZE_FFPG_CH1_RES_MEM 32'h800
`define BASE_FFPG_CH2_SET_MEM 16'h6000
`define SIZE_FFPG_CH2_SET_MEM 32'h800
`define BASE_FFPG_CH2_RES_MEM 16'h8000
`define SIZE_FFPG_CH2_RES_MEM 32'h800
hdl/svec/sim/testbench/SvecTopFfpgWrapper.vhd 0 → 100644
View file @ 41f6f13e
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.FfpgPkg.all;
entity SvecTopFfpgWrapper is
port (
-- Local 20MHz VCXO oscillator
Clk20_ik: in std_logic;
-- Reset from system fpga
Reset_inr: in std_logic;
-- DAC interface (20MHz and 25MHz VCXO)
Pll20DacDin_o: out std_logic;
Pll20DacSclk_o: out std_logic;
Pll20DacSync_on: out std_logic;
Pll25DacDin_o: out std_logic;
Pll25DacSclk_o: out std_logic;
Pll25DacSync_on: out std_logic;
-- Carrier font panel LEDs
FpLedsLineEnable_ob2: out std_logic_vector(1 downto 0);
FpLedsLine_ob2: out std_logic_vector(1 downto 0);
FpLedsColumn_ob4: out std_logic_vector(3 downto 0);
-- Carrier I2C eeprom
CarrierScl_io: inout std_logic;
CarrierSda_io: inout std_logic;
-- PCB revision
PcbRev_i: in std_logic_vector(4 downto 0);
-- Carrier 1-wire interface (DS18B20 thermometer + unique ID)
CarrierOneWire_io: inout std_logic;
------------------------------------------
-- VME interface
------------------------------------------
VmeWrite_n_i : in std_logic;
VmeSysreset_n_i : in std_logic;
VmeRetry_oe_o : out std_logic;
VmeRetry_n_o : out std_logic;
VmeLword_n_b : inout std_logic;
VmeIackout_n_o : out std_logic;
VmeIackin_n_i : in std_logic;
VmeIack_n_i : in std_logic;
VmeDtack_oe_o : out std_logic;
VmeDtack_n_o : out std_logic;
VmeDs_n_i : in std_logic_vector(1 downto 0);
VmeData_oe_n_o : out std_logic;
VmeData_dir_o : out std_logic;
VmeBerr_o : out std_logic;
VmeAs_n_i : in std_logic;
VmeAddr_oe_n_o : out std_logic;
VmeAddr_dir_o : out std_logic;
VmeIrq_n_o : out std_logic_vector(7 downto 1);
VmeGa_i : in std_logic_vector(5 downto 0);
VmeData_b : inout std_logic_vector(31 downto 0);
VmeAm_i : in std_logic_vector(5 downto 0);
VmeAddr_b : inout std_logic_vector(31 downto 1);
------------------------------------------
-- FMC slot management
------------------------------------------
Fmc0Present_in: in std_logic; -- Mezzanine present (active low)
-- Fmc0Scl: inout std_logic; -- Mezzanine system I2C clock (EEPROM)
-- Fmc0Sda: inout std_logic; -- Mezzanine system I2C data (EEPROM)
Fmc1Present_in: in std_logic; -- Mezzanine present (active low)
-- Fmc1Scl: inout std_logic; -- Mezzanine system I2C clock (EEPROM)
-- Fmc1Sda: inout std_logic; -- Mezzanine system I2C data (EEPROM)
------------------------------------------
-- FMC slot 0
------------------------------------------
-- clock
Fmc0ClkIn0P_ik: in std_logic;
Fmc0ClkIn0N_ik: in std_logic;
-- DACs
Fmc0TriggerDac_o_FrameSynchronization_n: out std_logic;
Fmc0TriggerDac_o_SerialClock: out std_logic;
Fmc0TriggerDac_o_SerialData: out std_logic;
Fmc0VcxoDac_o_FrameSynchronization_n: out std_logic;
Fmc0VcxoDac_o_SerialClock: out std_logic;
Fmc0VcxoDac_o_SerialData: out std_logic;
-- output enable
Fmc0Ch1OutputEnable_o: out std_logic;
Fmc0Ch2OutputEnable_o: out std_logic;
-- delay configuration
Fmc0DelayValue_ob: out std_logic_vector(9 downto 0);
Fmc0Ch1SetLe_o: out std_logic;
Fmc0Ch1ResLe_o: out std_logic;
Fmc0Ch2SetLe_o: out std_logic;
Fmc0Ch2ResLe_o: out std_logic;
Fmc0Ch1SetP_o: out std_logic;
Fmc0Ch1SetN_o: out std_logic;
Fmc0Ch1ResP_o: out std_logic;
Fmc0Ch1ResN_o: out std_logic;
Fmc0Ch2SetP_o: out std_logic;
Fmc0Ch2SetN_o: out std_logic;
Fmc0Ch2ResP_o: out std_logic;
Fmc0Ch2ResN_o: out std_logic;
Fmc0TriggerP_i: in std_logic;
Fmc0TriggerN_i: in std_logic;
-- AD9512 SPI
Fmc0SpiAd9512Sclk_o: out std_logic;
Fmc0SpiAd9512Mosi_o: out std_logic;
Fmc0SpiAd9512Miso_i: in std_logic;
Fmc0SpiAd9512Cs_on: out std_logic;
-- clock selection pin of SY58017U
Fmc0Clk2Sel_o: out std_logic;
-- temperature chip interface
Fmc0Onewire_io: inout std_logic;
-- LEDs
Fmc0Led_ob: out std_logic_vector(4 downto 1)
------------------------------------------
-- FMC slot 1
------------------------------------------
);
end entity;
architecture wrapper of SvecTopFfpgWrapper is
signal Fmc0TriggerDac_o, Fmc0VcxoDac_o: t_Ad5600Interface;
signal Fmc0DelayValue_ob_unsigned: unsigned(9 downto 0);
begin
cSvecTopFfpg: entity work.SvecTopFfpg(rtl)
port map (
Clk20_ik => Clk20_ik,
Reset_inr => Reset_inr,
Pll20DacDin_o => Pll20DacDin_o,
Pll20DacSclk_o => Pll20DacSclk_o,
Pll20DacSync_on => Pll20DacSync_on,
Pll25DacDin_o => Pll25DacDin_o,
Pll25DacSclk_o => Pll25DacSclk_o,
Pll25DacSync_on => Pll25DacSync_on,
FpLedsLineEnable_ob2 => FpLedsLineEnable_ob2,
FpLedsLine_ob2 => FpLedsLine_ob2,
FpLedsColumn_ob4 => FpLedsColumn_ob4,
CarrierScl_io => CarrierScl_io,
CarrierSda_io => CarrierSda_io,
PcbRev_i => PcbRev_i,
CarrierOneWire_io => CarrierOneWire_io,
------------------------------------------
-- VME interface
------------------------------------------
VmeWrite_n_i => VmeWrite_n_i,
VmeSysreset_n_i => VmeSysreset_n_i,
VmeRetry_oe_o => VmeRetry_oe_o,
VmeRetry_n_o => VmeRetry_n_o,
VmeLword_n_b => VmeLword_n_b,
VmeIackout_n_o => VmeIackout_n_o,
VmeIackin_n_i => VmeIackin_n_i,
VmeIack_n_i => VmeIack_n_i,
VmeDtack_oe_o => VmeDtack_oe_o,
VmeDtack_n_o => VmeDtack_n_o,
VmeDs_n_i => VmeDs_n_i,
VmeData_oe_n_o => VmeData_oe_n_o,
VmeData_dir_o => VmeData_dir_o,
VmeBerr_o => VmeBerr_o,
VmeAs_n_i => VmeAs_n_i,
VmeAddr_oe_n_o => VmeAddr_oe_n_o,
VmeAddr_dir_o => VmeAddr_dir_o,
VmeIrq_n_o => VmeIrq_n_o,
VmeGa_i => VmeGa_i,
VmeData_b => VmeData_b,
VmeAm_i => VmeAm_i,
VmeAddr_b => VmeAddr_b,
------------------------------------------
-- FMC slot management
------------------------------------------
Fmc0Present_in => Fmc0Present_in, -- Mezzanine present (active low)
Fmc1Present_in => Fmc1Present_in, -- Mezzanine present (active low)
------------------------------------------
-- FMC slot 0
------------------------------------------
Fmc0ClkIn0P_ik => Fmc0ClkIn0P_ik,
Fmc0ClkIn0N_ik => Fmc0ClkIn0N_ik,
Fmc0TriggerDac_o.FrameSynchronization_n => Fmc0TriggerDac_o_FrameSynchronization_n,
Fmc0TriggerDac_o.SerialClock => Fmc0TriggerDac_o_SerialClock,
Fmc0TriggerDac_o.SerialData => Fmc0TriggerDac_o_SerialData,
Fmc0VcxoDac_o.FrameSynchronization_n => Fmc0VcxoDac_o_FrameSynchronization_n,
Fmc0VcxoDac_o.SerialClock => Fmc0VcxoDac_o_SerialClock,
Fmc0VcxoDac_o.SerialData => Fmc0VcxoDac_o_SerialData,
Fmc0Ch1OutputEnable_o => Fmc0Ch1OutputEnable_o,
Fmc0Ch2OutputEnable_o => Fmc0Ch2OutputEnable_o,
Fmc0DelayValue_ob => Fmc0DelayValue_ob_unsigned,
Fmc0Ch1SetLe_o => Fmc0Ch1SetLe_o,
Fmc0Ch1ResLe_o => Fmc0Ch1ResLe_o,
Fmc0Ch2SetLe_o => Fmc0Ch2SetLe_o,
Fmc0Ch2ResLe_o => Fmc0Ch2ResLe_o,
Fmc0Ch1SetP_o => Fmc0Ch1SetP_o,
Fmc0Ch1SetN_o => Fmc0Ch1SetN_o,
Fmc0Ch1ResP_o => Fmc0Ch1ResP_o,
Fmc0Ch1ResN_o => Fmc0Ch1ResN_o,
Fmc0Ch2SetP_o => Fmc0Ch2SetP_o,
Fmc0Ch2SetN_o => Fmc0Ch2SetN_o,
Fmc0Ch2ResP_o => Fmc0Ch2ResP_o,
Fmc0Ch2ResN_o => Fmc0Ch2ResN_o,
Fmc0TriggerP_i => Fmc0TriggerP_i,
Fmc0TriggerN_i => Fmc0TriggerN_i,
Fmc0SpiAd9512Sclk_o => Fmc0SpiAd9512Sclk_o,
Fmc0SpiAd9512Mosi_o => Fmc0SpiAd9512Mosi_o,
Fmc0SpiAd9512Miso_i => Fmc0SpiAd9512Miso_i,
Fmc0SpiAd9512Cs_on => Fmc0SpiAd9512Cs_on,
Fmc0Clk2Sel_o => Fmc0Clk2Sel_o,
Fmc0Onewire_io => Fmc0Onewire_io,
Fmc0Led_ob => Fmc0Led_ob
);
Fmc0DelayValue_ob <= std_logic_vector(Fmc0DelayValue_ob_unsigned);
end architecture;
\ No newline at end of file
hdl/svec/sim/testbench/Testbench.sv 0 → 100644
View file @ 41f6f13e
`include "vme64x_bfm.svh"
`include "svec_vme_buffers.svh"
`include "fmc.svh"
`include "../../../ffpg/sim/testbench/ffpg_csr.svh"
`include "carrier_csr.svh"
module Testbench;
reg Reset_inr = 0;
reg Clk20_ik = 0;
always #25ns Clk20_ik <= ~Clk20_ik;
initial begin
#10us; // for PLL lock and reset settle
repeat(20) @(posedge Clk20_ik);
Reset_inr = 1;
end
IVME64X VME(Reset_inr);
`DECLARE_VME_BUFFERS(VME.slave);
`DECLARE_FMC(0);
logic Fmc1Present_in;
logic [1:0] FpLedsLineEnable_ob2;
logic [1:0] FpLedsLine_ob2;
logic [3:0] FpLedsColumn_ob4;
wire CarrierScl_io;
wire CarrierSda_io;
wire CarrierOneWire_io;
SvecTopFfpgWrapper cDut (
.Clk20_ik(Clk20_ik),
.Reset_inr(Reset_inr),
// Pll20DacDin_o: out std_logic;
// Pll20DacSclk_o: out std_logic;
// Pll20DacSync_on: out std_logic;
// Pll25DacDin_o: out std_logic;
// Pll25DacSclk_o: out std_logic;
// Pll25DacSync_on: out std_logic;
.FpLedsLineEnable_ob2(FpLedsLineEnable_ob2),
.FpLedsLine_ob2(FpLedsLine_ob2),
.FpLedsColumn_ob4(FpLedsColumn_ob4),
.CarrierScl_io(CarrierScl_io),
.CarrierSda_io(CarrierSda_io),
.PcbRev_i(5'b00001),
.CarrierOneWire_io(CarrierOneWire_io),
`WIRE_FMC(0)
.Fmc1Present_in(Fmc1Present_in),
`WIRE_VME_PINS(8) // slot number in parameter // don't change that magic 8 - it's hardcoded somewhere else
);
assign Fmc0Present_in = 1;
assign Fmc1Present_in = 0;
assign Fmc0ClkIn0P_ik = 0;
assign Fmc0ClkIn0N_ik = ~Fmc0ClkIn0P_ik;
assign Fmc0TriggerP_i = 0;
assign Fmc0TriggerN_i = ~Fmc0TriggerP_i;
assign Fmc0SpiAd9512Miso_i = 0;
task automatic init_vme64x_core(ref CBusAccessor_VME64x acc);
uint64_t rv;
/* map func0 to 0x80000000, A32 */
acc.write('h7ff63, 'h80, A32|CR_CSR|D08Byte3);
acc.write('h7ff67, 0, CR_CSR|A32|D08Byte3);
acc.write('h7ff6b, 0, CR_CSR|A32|D08Byte3);
acc.write('h7ff6f, 36, CR_CSR|A32|D08Byte3);
acc.write('h7ff33, 1, CR_CSR|A32|D08Byte3);
acc.write('h7fffb, 'h10, CR_CSR|A32|D08Byte3); /* enable module (BIT_SET = 0x10) */
acc.set_default_modifiers(A32 | D32 | SINGLE);
endtask
initial begin
uint64_t d;
uint32_t wr_data;
uint64_t blt_addr[];
uint64_t blt_data[];
uint32_t base;
uint32_t address;
int i, result;
CBusAccessor_VME64x acc;
acc = new(VME);
#10us; // for PLL lock and reset settle
#20us;
init_vme64x_core(acc);
base = 'h0;
$display("Carrier SDB:\n");
for (i=0; i<64; i = i+4) begin
address = base + i;
acc.read(address, d, A32|SINGLE|D32);
$display("[0x%x]: 0x%x\n", address, d[31:0]);
end
base = 'h2_0000 + 64*0;
$display("FFPG SDB:\n");
for (i=0; i<64; i = i+4) begin
address = base + i;
acc.read(address, d, A32|SINGLE|D32);
$display("[0x%x]: 0x%x\n", address, d[31:0]);
end
address = 'h2_0000 + 'h1_0000 + `ADDR_FFPG_STATUS;
$display("FFPG Status reg.:\n");
acc.read(address, d, A32|SINGLE|D32);
$display("[0x%x]: 0x%x\n", address, d[31:0]);
// $display("Release FMC0/1 reset\n");
// acc.write('h120C, 'h3, A32|SINGLE|D32);
// // Enable all interrupts
// $display("Enable FMC0 and FMC1 interrupt vectors\n");
// acc.write('h1308, 'h3, A32|SINGLE|D32);
// acc.read('h1310, d, A32|SINGLE|D32);
// $display("VIC interrupt mask = 0x%x\n",d);
// acc.write('h1300, 'h3, A32|SINGLE|D32);
// $display("Enable TRIGGER and END_ACQ in FMC0/1 EIC\n");
// acc.write('h2000, 'h3, A32|SINGLE|D32);
// acc.write('h6000, 'h3, A32|SINGLE|D32);
// // Trigger setup (sw trigger)
// $display("Trigger setup\n");
// acc.write('h5308, 'h8, A32|SINGLE|D32);
// // Acquisition setup
// $display("Acquisition setup\n");
// acc.write('h5320, 'h1, A32|SINGLE|D32); // 1 pre-trigger samples
// acc.write('h5324, 'hA, A32|SINGLE|D32); // 10 post-trigger samples
// acc.write('h5314, 'h1, A32|SINGLE|D32); // 1 shot
// // Make sure no acquisition is running
// acc.write('h5300, 'h2, A32|SINGLE|D32); // Send STOP command
// // Start acquisition
// $display("Start acquisition\n");
// acc.write('h5300, 'h1, A32|SINGLE|D32); // Send START command
// // Sw trigger
// #1us
// $display("Software trigger\n");
// acc.write('h5310, 'hFF, A32|SINGLE|D32);
// /*
// // Data "FIFO" test
// acc.write('h2200, 'h0, A32|SINGLE|D32);
// acc.read('h2200, d, A32|SINGLE|D32);
// $display("Read DDR_ADR: 0x%x\n", d);
// $display("Write data to DDR in BLT\n");
// blt_addr = {'h3000};
// blt_data = {'h1, 'h2, 'h3, 'h4, 'h5, 'h6, 'h7, 'h8 ,'h9, 'hA};
// acc.writem(blt_addr, blt_data, A32|BLT|D32, result);
// acc.write('h2200, 'h0, A32|SINGLE|D32);
// acc.read('h2200, d, A32|SINGLE|D32);
// $display("Read DDR_ADR: 0x%x\n", d);
// $display("Read data from DDR in BLT");
// blt_data = {};
// acc.readm(blt_addr, blt_data, A32|BLT|D32, result);
// for(i=0; i<10; i++)
// begin
// $display("Data %d: 0x%x\n", i, blt_data[i]);
// end
// */
// acc.write('h2200, 'h0, A32|SINGLE|D32);
// for(i=0; i<5; i++) begin
// acc.read('h3000, d, A32|SINGLE|D32);
// $display("Read %d: 0x%x\n", i, d);
// end
// acc.write('h2200, 'h0, A32|SINGLE|D32);
// for(i=0; i<2; i++) begin
// wr_data = i;
// acc.write('h3000, wr_data, A32|SINGLE|D32);
// $display("Write %d: 0x%x\n", i, wr_data);
// end
// acc.write('h2200, 'h0, A32|SINGLE|D32);
// for(i=0; i<5; i++) begin
// acc.read('h3000, d, A32|SINGLE|D32);
// $display("Read %d: 0x%x\n", i, d);
// end
$stop;
end
endmodule
hdl/svec/sim/testbench/components/sn74vmeh22501.v 0 → 100644
View file @ 41f6f13e
`timescale 1ns/1ns
module sn74vmeh22501 (
input oeab1,
oeby1_n,
a1,
output y1,
inout b1,
input oeab2,
oeby2_n,
a2,
output y2,
inout b2,
input oe_n,
input dir,
clkab,
le,
clkba,
inout [1:8] a3,
inout [1:8] b3);
assign b1 = oeab1 ? a1 : 1'bz;
assign y1 = oeby1_n ? 1'bz : b1;
assign b2 = oeab2 ? a2 : 1'bz;
assign y2 = oeby2_n ? 1'bz : b2;
reg [1:8] b3LFF;
always @(posedge clkab) if (~le) b3LFF <= #1 a3;
always @* if (le) b3LFF = a3;
assign b3 = (~oe_n && dir) ? b3LFF : 8'hz;
reg [1:8] a3LFF;
always @(posedge clkba) if (~le) a3LFF <= #1 b3;
always @* if (le) a3LFF = b3;
assign a3 = (~oe_n && ~dir) ? a3LFF : 8'hz;
endmodule
hdl/svec/sim/testbench/fmc.svh 0 → 100644
View file @ 41f6f13e
`define DECLARE_FMC(__nb) \
logic Fmc``__nb``ClkIn0P_ik; \
logic Fmc``__nb``ClkIn0N_ik; \
logic Fmc``__nb``TriggerDac_o_FrameSynchronization_n; \
logic Fmc``__nb``TriggerDac_o_SerialClock; \
logic Fmc``__nb``TriggerDac_o_SerialData; \
logic Fmc``__nb``VcxoDac_o_FrameSynchronization_n; \
logic Fmc``__nb``VcxoDac_o_SerialClock; \
logic Fmc``__nb``VcxoDac_o_SerialData; \
logic Fmc``__nb``Ch1OutputEnable_o; \
logic Fmc``__nb``Ch2OutputEnable_o; \
logic [9:0] Fmc``__nb``DelayValue_ob; \
logic Fmc``__nb``Ch1SetLe_o; \
logic Fmc``__nb``Ch1ResLe_o; \
logic Fmc``__nb``Ch2SetLe_o; \
logic Fmc``__nb``Ch2ResLe_o; \
logic Fmc``__nb``Ch1SetP_o; \
logic Fmc``__nb``Ch1SetN_o; \
logic Fmc``__nb``Ch1ResP_o; \
logic Fmc``__nb``Ch1ResN_o; \
logic Fmc``__nb``Ch2SetP_o; \
logic Fmc``__nb``Ch2SetN_o; \
logic Fmc``__nb``Ch2ResP_o; \
logic Fmc``__nb``Ch2ResN_o; \
logic Fmc``__nb``TriggerP_i; \
logic Fmc``__nb``TriggerN_i; \
logic Fmc``__nb``SpiAd9512Sclk_o; \
logic Fmc``__nb``SpiAd9512Mosi_o; \
logic Fmc``__nb``SpiAd9512Miso_i; \
logic Fmc``__nb``SpiAd9512Cs_on; \
logic Fmc``__nb``Clk2Sel_o; \
wire Fmc``__nb``Onewire_io; \
logic [4:1] Fmc``__nb``Led_ob; \
logic Fmc``__nb``Present_in;
`define WIRE_FMC(__nb) \
.Fmc``__nb``ClkIn0P_ik(Fmc``__nb``ClkIn0P_ik), \
.Fmc``__nb``ClkIn0N_ik(Fmc``__nb``ClkIn0N_ik), \
.Fmc``__nb``TriggerDac_o_FrameSynchronization_n(Fmc``__nb``TriggerDac_o_FrameSynchronization_n), \
.Fmc``__nb``TriggerDac_o_SerialClock(Fmc``__nb``TriggerDac_o_SerialClock), \
.Fmc``__nb``TriggerDac_o_SerialData(Fmc``__nb``TriggerDac_o_SerialData), \
.Fmc``__nb``VcxoDac_o_FrameSynchronization_n(Fmc``__nb``VcxoDac_o_FrameSynchronization_n), \
.Fmc``__nb``VcxoDac_o_SerialClock(Fmc``__nb``VcxoDac_o_SerialClock), \
.Fmc``__nb``VcxoDac_o_SerialData(Fmc``__nb``VcxoDac_o_SerialData), \
.Fmc``__nb``Ch1OutputEnable_o(Fmc``__nb``Ch1OutputEnable_o), \
.Fmc``__nb``Ch2OutputEnable_o(Fmc``__nb``Ch2OutputEnable_o), \
.Fmc``__nb``DelayValue_ob(Fmc``__nb``DelayValue_ob), \
.Fmc``__nb``Ch1SetLe_o(Fmc``__nb``Ch1SetLe_o), \
.Fmc``__nb``Ch1ResLe_o(Fmc``__nb``Ch1ResLe_o), \
.Fmc``__nb``Ch2SetLe_o(Fmc``__nb``Ch2SetLe_o), \
.Fmc``__nb``Ch2ResLe_o(Fmc``__nb``Ch2ResLe_o), \
.Fmc``__nb``Ch1SetP_o(Fmc``__nb``Ch1SetP_o), \
.Fmc``__nb``Ch1SetN_o(Fmc``__nb``Ch1SetN_o), \
.Fmc``__nb``Ch1ResP_o(Fmc``__nb``Ch1ResP_o), \
.Fmc``__nb``Ch1ResN_o(Fmc``__nb``Ch1ResN_o), \
.Fmc``__nb``Ch2SetP_o(Fmc``__nb``Ch2SetP_o), \
.Fmc``__nb``Ch2SetN_o(Fmc``__nb``Ch2SetN_o), \
.Fmc``__nb``Ch2ResP_o(Fmc``__nb``Ch2ResP_o), \
.Fmc``__nb``Ch2ResN_o(Fmc``__nb``Ch2ResN_o), \
.Fmc``__nb``TriggerP_i(Fmc``__nb``TriggerP_i), \
.Fmc``__nb``TriggerN_i(Fmc``__nb``TriggerN_i), \
.Fmc``__nb``SpiAd9512Sclk_o(Fmc``__nb``SpiAd9512Sclk_o), \
.Fmc``__nb``SpiAd9512Mosi_o(Fmc``__nb``SpiAd9512Mosi_o), \
.Fmc``__nb``SpiAd9512Miso_i(Fmc``__nb``SpiAd9512Miso_i), \
.Fmc``__nb``SpiAd9512Cs_on(Fmc``__nb``SpiAd9512Cs_on), \
.Fmc``__nb``Clk2Sel_o(Fmc``__nb``Clk2Sel_o), \
.Fmc``__nb``Onewire_io(Fmc``__nb``Onewire_io), \
.Fmc``__nb``Led_ob(Fmc``__nb``Led_ob), \
.Fmc``__nb``Present_in(Fmc``__nb``Present_in),
hdl/svec/sim/testbench/make 0 → 100644
View file @ 41f6f13e
# clean working space and compile all necessary files
# I want the HDLmake to run under Windows!
vlib work
vdel -lib work -all
vlib work
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/wishbone-gen/lib/wbgen2_pkg.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/wishbone-gen/lib/wbgen2_dpssram.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/wishbone-gen/lib/wbgen2_eic.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/wishbone-gen/lib/wbgen2_fifo_async.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/wishbone-gen/lib/wbgen2_fifo_sync.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/PulseGenerator.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/PulseGeneratorTime.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/Counter.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/CounterLength.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/ShiftRegister.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/ResetSyncer.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/Delay.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/EdgeDetector.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/Reg.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/RegSyncer.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/SlowToggle.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
vlog -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v
vlog -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v
vlog -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd
vlog -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/FfpgPkg.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/ffpg_csr_pkg.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/ffpg_csr.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/WbSlaveWrapper.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/DelayController.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/DacsController.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/DelayedPulseGenerator/Fsm.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/DelayedPulseGenerator/ClkRfDomain.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/DelayedPulseGenerator/DelayedPulseGenerator.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/FfpgSlave.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/FfpgCore.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/vme64x_pack.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_pack.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CSR_pack.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CRAM.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_IRQ_Controller.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_SharedComps.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Init.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Am_Match.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Funct_Match.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Access_Decode.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Wb_master.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_swapper.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_bus.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME64xCore_Top.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/common/gc_sync_register.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/genrams/generic/inferred_async_fifo.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/carrier_csr.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/HeartBeat.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/SvecTopFfpg.vhd
vcom -2008 -reportprogress 300 -work work SvecTopFfpgWrapper.vhd
vlog -reportprogress 300 -work work Testbench.sv +incdir+../../../ip_cores/general-cores/sim
hdl/svec/sim/testbench/re 0 → 100644
View file @ 41f6f13e
# recompile and restart with new random seed
#do make
vlog -reportprogress 300 -work work Testbench.sv +incdir+../../../ip_cores/general-cores/sim
do res
\ No newline at end of file
hdl/svec/sim/testbench/res 0 → 100644
View file @ 41f6f13e
# restart simulation with new random seed
restart -force -sv_seed random
run -all
\ No newline at end of file
hdl/svec/sim/testbench/sim 0 → 100644
View file @ 41f6f13e
# start simulation, set waveform, run simulation
vsim -voptargs=+acc work.Testbench
# add wave -group Interface -r sim:/Testbench/LocalInterface/*
add wave -group DUT sim:/Testbench/cDut/cSvecTopFfpg/*
add wave -group Xbar sim:/Testbench/cDut/cSvecTopFfpg/cWbSdbCrossbar/*
# add wave -group WbSlave -r sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cWbSlaveWrapper/*
# add wave -group DacsController sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDacsController/*
# add wave -group DelayController -r sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayController/*
#
# add wave -group DelayedPulseGeneratorCh1 sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh1/*
# add wave -group DelayedPulseGeneratorCh1 -group ClkRfDomain sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh1/cClkRfDomain/*
# add wave -group DelayedPulseGeneratorCh1 -group ClkRfDomain -group Fsm sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh1/cClkRfDomain/cFsm/*
# add wave -group DelayedPulseGeneratorCh1 -group ClkRfDomain -group BitCounter sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh1/cClkRfDomain/cBitCounter/*
# add wave -group DelayedPulseGeneratorCh1 -group ClkRfDomain -group StreamCounter sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh1/cClkRfDomain/cStreamCounter/*
# add wave -group DelayedPulseGeneratorCh1 -group ClkRfDomain -group ShiftRegisterSet sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh1/cClkRfDomain/cShiftRegisterSet/*
# add wave -group DelayedPulseGeneratorCh1 -group ClkRfDomain -group ShiftRegisterReset sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh1/cClkRfDomain/cShiftRegisterReset/*
#
# add wave -group DelayedPulseGeneratorCh2 sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh2/*
# add wave -group DelayedPulseGeneratorCh2 -group ClkRfDomain sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh2/cClkRfDomain/*
# add wave -group DelayedPulseGeneratorCh2 -group ClkRfDomain -group Fsm sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh2/cClkRfDomain/cFsm/*
# add wave -group DelayedPulseGeneratorCh2 -group ClkRfDomain -group BitCounter sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh2/cClkRfDomain/cBitCounter/*
# add wave -group DelayedPulseGeneratorCh2 -group ClkRfDomain -group StreamCounter sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh2/cClkRfDomain/cStreamCounter/*
# add wave -group DelayedPulseGeneratorCh2 -group ClkRfDomain -group ShiftRegisterSet sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh2/cClkRfDomain/cShiftRegisterSet/*
# add wave -group DelayedPulseGeneratorCh2 -group ClkRfDomain -group ShiftRegisterReset sim:/Testbench/dut/cFfpgCore/cFfpgSlave/cDelayedPulseGeneratorCh2/cClkRfDomain/cShiftRegisterReset/*
configure wave -namecolwidth 217
configure wave -valuecolwidth 100
configure wave -signalnamewidth 1
sv_reseed random
set NumericStdNoWarnings 1
set StdArithNoWarnings 1
run -all
# set NumericStdNoWarnings 0
# set StdArithNoWarnings 1
wave zoomfull
hdl/svec/sim/testbench/svec_vme_buffers.svh 0 → 100644
View file @ 41f6f13e
`include "components/sn74vmeh22501.v"
`include "vme64x_bfm.svh"
module bidir_buf(
a,
b,
dir, /* 0: a->b, 1: b->a */
oe_n );
parameter g_width = 1;
inout [g_width-1:0] a,b;
input dir, oe_n;
assign b = (!dir && !oe_n) ? a : 'bz;
assign a = (dir && !oe_n) ? b : 'bz;
endmodule // bidir_buf
module svec_vme_buffers (
output VME_AS_n_o,
output VME_RST_n_o,
output VME_WRITE_n_o,
output [5:0] VME_AM_o,
output [1:0] VME_DS_n_o,
output [5:0] VME_GA_o,
input VME_BERR_i,
input VME_DTACK_n_i,
input VME_RETRY_n_i,
input VME_RETRY_OE_i,
inout VME_LWORD_n_b,
inout [31:1] VME_ADDR_b,
inout [31:0] VME_DATA_b,
output VME_BBSY_n_o,
input [6:0] VME_IRQ_n_i,
output VME_IACKIN_n_o,
input VME_IACKOUT_n_i,
output VME_IACK_n_o,
input VME_DTACK_OE_i,
input VME_DATA_DIR_i,
input VME_DATA_OE_N_i,
input VME_ADDR_DIR_i,
input VME_ADDR_OE_N_i,
IVME64X.slave slave
);
pullup(slave.as_n);
pullup(slave.rst_n);
pullup(slave.irq_n[0]);
pullup(slave.irq_n[1]);
pullup(slave.irq_n[2]);
pullup(slave.irq_n[3]);
pullup(slave.irq_n[4]);
pullup(slave.irq_n[5]);
pullup(slave.irq_n[6]);
pullup(slave.iack_n);
pullup(slave.dtack_n);
pullup(slave.retry_n);
pullup(slave.ds_n[1]);
pullup(slave.ds_n[0]);
pullup(slave.lword_n);
pullup(slave.berr_n);
pullup(slave.write_n);
pulldown(slave.bbsy_n);
pullup(slave.iackin_n);
assign VME_RST_n_o = slave.rst_n;
assign VME_AS_n_o = slave.as_n;
assign VME_GA_o = slave.ga;
assign VME_WRITE_n_o = slave.write_n;
assign VME_AM_o = slave.am;
assign VME_DS_n_o = slave.ds_n;
assign VME_BBSY_n_o = slave.bbsy_n;
assign VME_IACKIN_n_o = slave.iackin_n;
assign VME_IACK_n_o = slave.iack_n;
bidir_buf #(1) b0 (slave.lword_n, VME_LWORD_n_b, VME_ADDR_DIR_i, VME_ADDR_OE_N_i);
bidir_buf #(31) b1 (slave.addr, VME_ADDR_b, VME_ADDR_DIR_i, VME_ADDR_OE_N_i);
bidir_buf #(32) b2 (slave.data, VME_DATA_b, VME_DATA_DIR_i, VME_DATA_OE_N_i);
pulldown(VME_BERR_i);
pulldown(VME_ADDR_DIR_i);
pulldown(VME_ADDR_OE_N_i);
pulldown(VME_DATA_DIR_i);
pulldown(VME_DATA_OE_N_i);
assign slave.dtack_n = VME_DTACK_n_i;
assign slave.berr_n = ~VME_BERR_i;
assign slave.retry_n = VME_RETRY_n_i;
endmodule
`define DECLARE_VME_BUFFERS(iface) \
wire VME_AS_n;\
wire VME_RST_n;\
wire VME_WRITE_n;\
wire [5:0] VME_AM;\
wire [1:0] VME_DS_n;\
wire VME_BERR;\
wire VME_DTACK_n;\
wire VME_RETRY_n;\
wire VME_RETRY_OE;\
wire VME_LWORD_n;\
wire [31:1]VME_ADDR;\
wire [31:0]VME_DATA;\
wire VME_BBSY_n;\
wire [6:0]VME_IRQ_n;\
wire VME_IACKIN_n,VME_IACK_n;\
wire VME_IACKOUT_n;\
wire VME_DTACK_OE;\
wire VME_DATA_DIR;\
wire VME_DATA_OE_N;\
wire VME_ADDR_DIR;\
wire VME_ADDR_OE_N;\
svec_vme_buffers U_VME_Bufs ( \
.VME_AS_n_o(VME_AS_n),\
.VME_RST_n_o(VME_RST_n),\
.VME_WRITE_n_o(VME_WRITE_n),\
.VME_AM_o(VME_AM),\
.VME_DS_n_o(VME_DS_n),\
.VME_BERR_i(VME_BERR),\
.VME_DTACK_n_i(VME_DTACK_n),\
.VME_RETRY_n_i(VME_RETRY_n),\
.VME_RETRY_OE_i(VME_RETRY_OE),\
.VME_LWORD_n_b(VME_LWORD_n),\
.VME_ADDR_b(VME_ADDR),\
.VME_DATA_b(VME_DATA),\
.VME_IRQ_n_i(VME_IRQ_n),\
.VME_IACK_n_o(VME_IACK_n),\
.VME_IACKIN_n_o(VME_IACKIN_n),\
.VME_IACKOUT_n_i(VME_IACKOUT_n),\
.VME_DTACK_OE_i(VME_DTACK_OE),\
.VME_DATA_DIR_i(VME_DATA_DIR),\
.VME_DATA_OE_N_i(VME_DATA_OE_N),\
.VME_ADDR_DIR_i(VME_ADDR_DIR),\
.VME_ADDR_OE_N_i(VME_ADDR_OE_N),\
.slave(iface)\
);
function automatic bit[5:0] _gen_ga(int slot);
bit[4:0] slot_id = slot;
return {^slot_id, ~slot_id};
endfunction // _gen_ga
`define WIRE_VME_PINS(slot_id) \
.VmeAs_n_i(VME_AS_n),\
.VmeSysreset_n_i(VME_RST_n),\
.VmeWrite_n_i(VME_WRITE_n),\
.VmeAm_i(VME_AM),\
.VmeDs_n_i(VME_DS_n),\
.VmeGa_i(_gen_ga(slot_id)),\
.VmeBerr_o(VME_BERR),\
.VmeDtack_n_o(VME_DTACK_n),\
.VmeRetry_n_o(VME_RETRY_n),\
.VmeRetry_oe_o(VME_RETRY_OE),\
.VmeLword_n_b(VME_LWORD_n),\
.VmeAddr_b(VME_ADDR),\
.VmeData_b(VME_DATA),\
.VmeIrq_n_o(VME_IRQ_n),\
.VmeIack_n_i(VME_IACK_n),\
.VmeIackin_n_i(VME_IACKIN_n),\
.VmeIackout_n_o(VME_IACKOUT_n),\
.VmeDtack_oe_o(VME_DTACK_OE),\
.VmeData_dir_o(VME_DATA_DIR),\
.VmeData_oe_n_o(VME_DATA_OE_N),\
.VmeAddr_dir_o(VME_ADDR_DIR),\
.VmeAddr_oe_n_o(VME_ADDR_OE_N)
hdl/svec/sim/testbench/vme64x_bfm.svh 0 → 100644
View file @ 41f6f13e
This diff is collapsed.
hdl/svec/wb_gen/Makefile
View file @ 41f6f13e
WBGEN2=wbgen2
RTL=../rtl/
DOC=../../../doc/manual/svec/
SIM=../sim/testbench/
%:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $(DOC)$@.htm -C $@.h $@.wb
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $(DOC)$@.htm -C $@.h -K $(SIM)$@.svh $@.wb
$(WBGEN2) -f texinfo -D $(DOC)$@.tex $@.wb
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