wr_softpll_ng: improved CDC logic. Fixes rare no-locks/FIFO errors, likely due to synthesizer doing some weird cross-clock-domains logic optimizations

... with the input clock

wr_core: add generic for reverse DDMTD operation
wr_gtx_phy_kintex7_lp: make 'reversed' DDMTD operation a generic

boards: fix incorrect logic of reset input for aasd

See merge request !8

The arst_i input of gc_reset_multi_aasd is active high,
so the resets must be or-ed (using positive logic)

Remove unused led_green and led_red, regenerate
Generate H header with struct (instead of offsets)

to ease connection with records

Peter lpdc mdio regs generalize

See merge request !7

Avoid the generation of a latch during synthesis

See merge request !2

expose phy_mdio_master interface on xwrc_board_common

See merge request !6

To ease the use of the record variants

timing/pulse_stamper: replace hand-written CDC chains with gc_[sync|pulse_synchronizer] for the ease of constraint definition

wr_softpll_ng: remove builtin frequency monitor, as the WRPCv5 will have a full blown FreqMon core integrated

it has never been really finished to be useful

timing: add enable (mask) input to dmtd_sampler

wr_gtx_phy_virtex6_lp: increase link down detect threshold so the LPDC PHY does…

See merge request !5

wr_gtx_phy_virtex6_lp: increase link down detect threshold so the LPDC PHY does not fail on jumbo frames