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White Rabbit core collection
Commit 91ea0ab0 authored by Tristan Gingold's avatar Tristan Gingold
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wrc_core: add g_hwbld_date generic

parent 6f867f11
Pipeline #4625 failed with stage
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    Showing with 13 additions and 6 deletions
    modules/wrc_core/wr_core.vhd
    View file @ 91ea0ab0
    ......@@ -108,7 +108,8 @@ entity wr_core is
    g_diag_rw_size : integer := 0;
    g_dac_bits : integer := 16;
    g_softpll_aux_channel_config : t_softpll_channels_config_array := c_softpll_default_channels_config;
    g_with_clock_freq_monitor : boolean := true
    g_with_clock_freq_monitor : boolean := true;
    g_hwbld_date : std_logic_vector(31 downto 0) := (others => 'X')
    );
    port(
    ---------------------------------------------------------------------------
    ......@@ -874,7 +875,7 @@ begin
    -----------------------------------------------------------------------------
    -- WB Peripherials
    -----------------------------------------------------------------------------
    PERIPH : wrc_periph
    PERIPH : entity work.wrc_periph
    generic map(
    g_board_name => g_board_name,
    g_flash_secsz_kb => g_flash_secsz_kb,
    ......@@ -890,7 +891,8 @@ begin
    g_diag_id => g_diag_id,
    g_diag_ver => g_diag_ver,
    g_diag_ro_size => g_diag_ro_size,
    g_diag_rw_size => g_diag_rw_size)
    g_diag_rw_size => g_diag_rw_size,
    g_hwbld_date => g_hwbld_date)
    port map(
    clk_sys_i => clk_sys_i,
    rst_n_i => rst_n_i,
    ......
    modules/wrc_core/wrc_periph.vhd
    View file @ 91ea0ab0
    ......@@ -61,7 +61,8 @@ entity wrc_periph is
    g_diag_ver : integer := 0;
    g_diag_ro_size : integer := 0;
    g_diag_rw_size : integer := 0;
    g_wdiags_num_words : integer := 64);
    g_wdiags_num_words : integer := 64;
    g_hwbld_date : std_logic_vector(31 downto 0));
    port(
    clk_sys_i : in std_logic;
    rst_n_i : in std_logic;
    ......@@ -332,6 +333,8 @@ begin
    sysc_regs_i.gpsr_spi_miso_i <= spi_miso_i;
    sysc_regs_i.hwbld_date_i <= g_hwbld_date;
    -------------------------------------
    -- DIAG to/from external modules
    -------------------------------------
    ......
    modules/wrc_core/xwr_core.vhd
    View file @ 91ea0ab0
    ......@@ -106,7 +106,8 @@ entity xwr_core is
    g_diag_rw_size : integer := 0;
    g_dac_bits : integer := 16;
    g_softpll_aux_channel_config : t_softpll_channels_config_array := c_softpll_default_channels_config;
    g_with_clock_freq_monitor : boolean := true
    g_with_clock_freq_monitor : boolean := true;
    g_hwbld_date : std_logic_vector(31 downto 0) := (others => 'X')
    );
    port(
    ---------------------------------------------------------------------------
    ......@@ -323,7 +324,8 @@ begin
    g_dac_bits => g_dac_bits,
    g_use_platform_specific_dpram => g_use_platform_specific_dpram,
    g_softpll_aux_channel_config => g_softpll_aux_channel_config,
    g_with_clock_freq_monitor => g_with_clock_freq_monitor
    g_with_clock_freq_monitor => g_with_clock_freq_monitor,
    g_hwbld_date => g_hwbld_date
    )
    port map(
    clk_sys_i => clk_sys_i,
    ......
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