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White Rabbit core collection
Commit 2e901984 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Tristan Gingold
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wr_endpoint: various CDC fixes

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modules/wr_endpoint/ep_rx_pcs_16bit.vhd
View file @ 2e901984
......@@ -6,7 +6,6 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-16
-- Last update: 2023-03-13
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -19,20 +18,20 @@
--
-- Copyright (c) 2011-2017 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
......@@ -79,7 +78,7 @@ entity ep_rx_pcs_16bit is
-------------------------------------------------------------------------------
-- PHY interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
phy_rdy_i : in std_logic;
phy_rx_clk_i : in std_logic;
......@@ -89,7 +88,7 @@ entity ep_rx_pcs_16bit is
-------------------------------------------------------------------------------
-- Wishbone registers
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Receive control regsiter
mdio_mcr_reset_i : in std_logic;
......@@ -110,7 +109,7 @@ entity ep_rx_pcs_16bit is
rmon_rx_overrun : out std_logic;
rmon_rx_inv_code : out std_logic;
rmon_rx_sync_lost : out std_logic;
nice_dbg_o : out t_dbg_ep_rxpcs
);
......@@ -194,6 +193,7 @@ architecture behavioral of ep_rx_pcs_16bit is
signal rx_sync_enable : std_logic;
signal lcr_ready : std_logic;
signal lcr_ready_d : std_logic;
signal lcr_prev_val : std_logic_vector(15 downto 0);
signal lcr_cur_val : std_logic_vector(15 downto 0);
signal lcr_final_val : std_logic_vector(15 downto 0);
......@@ -261,7 +261,7 @@ begin
ppulse_o => open);
U_sync_power_down : gc_sync_ffs
generic map (
g_sync_edge => "positive")
......@@ -326,6 +326,14 @@ begin
synced_o <= rx_sync_status; -- drive the PCS outputs
sync_lost_o <= rx_sync_lost_p;
p_delay_lcr_ready : process (phy_rx_clk_i)
begin
if rising_edge(phy_rx_clk_i) then
lcr_ready_d <= lcr_ready;
end if;
end process;
-------------------------------------------------------------------------------
-- Calibration pattern logic
-------------------------------------------------------------------------------
......@@ -366,10 +374,10 @@ begin
end process;
-------------------------------------------------------------------------------
-- Clock adjustment FIFO
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
phy_rx_data_shrunk <= d_data(7 downto 0) & phy_rx_data_i(15 downto 8);
phy_rx_data_muxed <= phy_rx_data_i when odd_reception = '0' else
......@@ -382,7 +390,7 @@ begin
p_8b10b_postprocess : process(phy_rx_clk_i)
begin
if rising_edge(phy_rx_clk_i) then
if(rst_n_rx = '0' or rx_synced = '0') then
d_data <= (others => '0');
d_is_idle <= '0';
......@@ -401,14 +409,14 @@ begin
d_data <= phy_rx_data_i;
d_is_k <= phy_rx_k_i;
d_data_shrunk <= d_data(7 downto 0) & phy_rx_data_i(15 downto 8); --
d_data_shrunk <= d_data(7 downto 0) & phy_rx_data_i(15 downto 8); --
d_is_k_shrunk <= d_is_k(0) & phy_rx_k_i(1);
if(phy_rx_enc_err_i = '0') then
d_err <= '0';
d_is_idle <= f_to_sl(phy_rx_data_i(15 downto 8) = c_K28_5
and (phy_rx_data_i(7 downto 0) = c_d16_2
or phy_rx_data_i(7 downto 0) = c_d5_6)
......@@ -468,13 +476,14 @@ begin
end if;
end process;
-- process: RBCLK-driven RX state machine. Implements the receive logic od 802.3z compliant
-- 1000BaseX PCS.
-- reads: almost everything
-- writes: almost everything
rx_fsm : process (phy_rx_clk_i)
p_rx_fsm : process (phy_rx_clk_i)
begin
if rising_edge(phy_rx_clk_i) then
-- reset or PCS disabled
......@@ -516,12 +525,12 @@ begin
-------------------------------------------------------------------------------
-- Main RX PCS state machine
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
case rx_state is
-------------------------------------------------------------------------------
-- State NOFRAME: receiver is receiving IDLE pattern
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
when RX_NOFRAME =>
preamble_cntr <= "011";
......@@ -595,7 +604,7 @@ begin
-------------------------------------------------------------------------------
-- States CR3/CR4: reception of LCR register value.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
when RX_CR => -- receives the 1st byte of Config_Reg and
-- checks if the subsequent Config_Reg
-- values are identical.
......@@ -638,7 +647,7 @@ begin
-------------------------------------------------------------------------------
-- State SPD_PREAMBLE: we've received an Start-Of-Packet delimeter. Check for
-- the valid preamble.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
when RX_SPD_PREAMBLE =>
rx_busy <= '1';
......@@ -663,7 +672,7 @@ begin
pcs_fab_out.sof <= '1';
rx_state <= RX_PAYLOAD;
end if;
elsif (d_is_preamble = '1') then
preamble_cntr <= preamble_cntr - 1;
-- got duplicated SPD code?
......@@ -705,7 +714,7 @@ begin
pcs_fab_out.error <= '1';
pcs_fab_out.dvalid <= '0';
pcs_fab_out.bytesel <= 'X';
rmon_invalid_code_p_int <= d_err;
rmon_rx_overrun_p_int <= pcs_fifo_almostfull_i;
......@@ -723,7 +732,7 @@ begin
pcs_fab_out.dvalid <= '0';
rx_state <= RX_EXTEND;
end if;
else
pcs_fab_out.bytesel <= '0';
pcs_fab_out.error <= '0';
......@@ -761,10 +770,17 @@ begin
end if;
end case;
end if;
end if;
end if;
end process;
an_rx_val_o <= lcr_final_val;
U_Sync_an_rx_value: entity work.gc_sync_register
generic map (
g_width => 16)
port map (
clk_i => clk_sys_i,
rst_n_a_i => rst_n_i,
d_i => lcr_final_val,
q_o => an_rx_val_o);
U_sync_an_rx_ready : gc_sync_ffs
generic map (
......@@ -772,7 +788,7 @@ begin
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
data_i => lcr_ready,
data_i => lcr_ready_d,
synced_o => an_rx_valid_o,
npulse_o => open,
ppulse_o => open);
......@@ -807,7 +823,7 @@ begin
extended_o => rmon_rx_overrun);
-- drive the "RX PCS Sync Lost" event counter
rmon_rx_sync_lost <= rx_sync_lost_p and (not mdio_mcr_pdown_i);
rmon_rx_sync_lost <= rx_sync_lost_p and (not mdio_mcr_pdown_rx_clk);
pcs_fab_out.rx_timestamp_valid <= timestamp_valid_i;
......@@ -821,5 +837,3 @@ begin
pcs_fab_o <= pcs_fab_out;
end behavioral;
modules/wr_endpoint/ep_rx_pcs_8bit.vhd
View file @ 2e901984
......@@ -851,7 +851,7 @@ begin
extended_o => rmon_rx_overrun);
-- drive the "RX PCS Sync Lost" event counter
rmon_rx_sync_lost <= rx_sync_lost_p and (not mdio_mcr_pdown_i);
rmon_rx_sync_lost <= rx_sync_lost_p and (not mdio_mcr_pdown_synced);
end behavioral;
......
modules/wr_endpoint/ep_timestamping_unit.vhd
View file @ 2e901984
-------------------------------------------------------------------------------
-- Title : Optical 1000base-X endpoint - IEEE1588/WhiteRabbit
-- timestamping unit
-- Project : White Rabbit
-- Project : White Rabbit
-------------------------------------------------------------------------------
-- File : ep_timestamping_unit.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-22
-- Last update: 2017-02-03
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -23,20 +22,20 @@
--
-- Copyright (c) 2009 - 2012 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
......@@ -106,7 +105,7 @@ entity ep_timestamping_unit is
-------------------------------------------------------------------------------
-- TX Timestamp output (clk_ref_i clock domain)
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- TX timestamp output (to TXTSU/Framer)
txts_timestamp_o : out std_logic_vector(31 downto 0);
......@@ -187,8 +186,10 @@ architecture syn of ep_timestamping_unit is
signal rx_trigger_mask, rx_trigger_a, rx_cal_pulse_a : std_logic;
signal regs_o_tscr_cs_done : std_logic;
signal regs_o_tscr_rx_cal_result_rx_clk : std_logic;
signal regs_o_tscr_rx_cal_result : std_logic;
signal regs_i_tscr_en_rxts_rx_clk : std_logic;
begin -- syn
-- Instatniation of the timestamping counter
......@@ -229,7 +230,7 @@ begin -- syn
cal_count <= (others => '0');
rx_cal_pulse_a <= '0';
rx_trigger_mask <= '1';
elsif(regs_i.tscr_rx_cal_start_o = '1') then
cal_count <= to_unsigned(1, 6);
rx_trigger_mask <= '0';
......@@ -238,14 +239,14 @@ begin -- syn
if(rx_ts_done = '1') then
if(cntr_rx_f /= cntr_rx_r(g_timestamp_bits_f-1 downto 0)) then
regs_o_tscr_rx_cal_result <= '1';
regs_o_tscr_rx_cal_result_rx_clk <= '1';
else
regs_o_tscr_rx_cal_result <= '0';
regs_o_tscr_rx_cal_result_rx_clk <= '0';
end if;
end if;
else
rx_trigger_mask <= '1';
end if;
......@@ -254,7 +255,7 @@ begin -- syn
else
rx_cal_pulse_a <= '0';
end if;
end if;
end process;
......@@ -273,7 +274,7 @@ begin -- syn
ppulse_o => take_tx_synced_p);
sync_ffs_rx_r : gc_sync_ffs
generic map (
g_sync_edge => "positive")
......@@ -308,7 +309,8 @@ begin -- syn
npulse_o => open,
ppulse_o => take_rx_synced_p_fedge);
take_r : process(clk_ref_i)
begin
......@@ -337,7 +339,7 @@ begin -- syn
else
tx_sync_delay <= '0' & tx_sync_delay(tx_sync_delay'length-1 downto 1);
end if;
end if;
end if;
end process;
......@@ -371,8 +373,8 @@ begin -- syn
synced_o => open,
npulse_o => tx_ts_done,
ppulse_o => open);
-- timestamping "out" signals sync chains (clk_ref -> clk_ref)
-- timestamping "out" signals sync chains (clk_ref -> clk_ref)
tx_out_gen : gc_sync_ffs
generic map (
g_sync_edge => "positive")
......@@ -396,6 +398,20 @@ begin -- syn
npulse_o => rx_ts_done,
ppulse_o => open);
inst_sync_en_rxts : gc_sync
port map (
clk_i => clk_rx_i,
rst_n_a_i => rst_n_rx_i,
d_i => regs_i.tscr_en_rxts_o,
q_o => regs_i_tscr_en_rxts_rx_clk );
inst_sync_rx_cal_result : gc_sync
port map (
clk_i => clk_sys_i,
rst_n_a_i => rst_n_sys_i,
d_i => regs_o_tscr_rx_cal_result_rx_clk,
q_o => regs_o_tscr_rx_cal_result );
txts_o <= txts; -- 2013-Nov-28 peterj added for debugging/calibration
rxts_o <= rx_ts_done; -- 2013-Nov-28 peterj added for debugging/calibration
......@@ -407,9 +423,9 @@ begin -- syn
rxts_timestamp_o <= (others => '0');
rxts_timestamp_valid_o <= '0';
else
if(regs_i. tscr_en_rxts_o = '0') then
if(regs_i_tscr_en_rxts_rx_clk = '0') then
rxts_timestamp_stb_o <= '0';
elsif(rx_ts_done = '1' and regs_i.tscr_en_rxts_o = '1') then
elsif(rx_ts_done = '1' and regs_i_tscr_en_rxts_rx_clk = '1') then
rxts_timestamp_stb_o <= '1';
rxts_timestamp_valid_o <= valid_rx;
rxts_timestamp_o <= cntr_rx_f & cntr_rx_r;
......
modules/wr_endpoint/ep_tx_pcs_16bit.vhd
View file @ 2e901984
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