wrc_core: fix likely typo on ppsg_timing_ok

eb413a57 · Tomasz Wlostowski · Tristan Gingold · ec0b9a5a · eb413a57
Commit eb413a57 authored May 30, 2023 by Tomasz Wlostowski Committed by Tristan Gingold Jun 05, 2023
Hide whitespace changes
Inline Side-by-side

Showing with 2 additions and 2 deletions

wr_core.vhd modules/wrc_core/wr_core.vhd +2 -2

No files found.
--- a/modules/wrc_core/wr_core.vhd
+++ b/modules/wrc_core/wr_core.vhd
@@ -6,7 +6,6 @@
 -- Author     : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Created    : 2011-02-02
-- Last update: 2023-05-05
 -- Platform   : FPGA-generics
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
@@ -629,7 +628,8 @@ begin
      tm_cycles_o     => tm_cycles_o,
      tm_time_valid_o => tm_time_valid_o
      );
-  ppsg_link_ok <= not phy_rst;
+
+  ppsg_link_ok <= ep_led_link;
  pps_csync_o  <= s_pps_csync;
  pps_valid_o  <= pps_valid;