Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
W
White Rabbit core collection
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
30
Issues
30
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Schedules
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
White Rabbit core collection
Commits
8feb29dc
Commit
8feb29dc
authored
Jun 06, 2023
by
Tristan Gingold
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
wrc_core: remove unused led_green and led_red
parent
3c5cf0df
Hide whitespace changes
Inline
Side-by-side
Showing
3 changed files
with
0 additions
and
28 deletions
+0
-28
wr_core.vhd
modules/wrc_core/wr_core.vhd
+0
-2
wrc_periph.vhd
modules/wrc_core/wrc_periph.vhd
+0
-23
wrcore_pkg.vhd
modules/wrc_core/wrcore_pkg.vhd
+0
-3
No files found.
modules/wrc_core/wr_core.vhd
View file @
8feb29dc
...
...
@@ -897,8 +897,6 @@ begin
rst_net_n_o
=>
rst_net_n
,
rst_wrc_n_o
=>
rst_wrc_n
,
led_red_o
=>
open
,
--led_red_o,
led_green_o
=>
open
,
--led_green_o,
scl_o
=>
scl_o
,
scl_i
=>
scl_i
,
sda_o
=>
sda_o
,
...
...
modules/wrc_core/wrc_periph.vhd
View file @
8feb29dc
...
...
@@ -6,7 +6,6 @@
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-04-04
-- Last update: 2023-04-26
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
...
...
@@ -70,8 +69,6 @@ entity wrc_periph is
rst_net_n_o
:
out
std_logic
;
rst_wrc_n_o
:
out
std_logic
;
led_red_o
:
out
std_logic
;
led_green_o
:
out
std_logic
;
scl_o
:
out
std_logic
;
scl_i
:
in
std_logic
;
sda_o
:
out
std_logic
;
...
...
@@ -185,26 +182,6 @@ begin
end
if
;
end
process
;
-------------------------------------
-- LEDs
-------------------------------------
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
if
(
sysc_regs_o
.
gpsr_led_link_o
=
'1'
)
then
led_red_o
<=
'1'
;
elsif
(
sysc_regs_o
.
gpcr_led_link_o
=
'1'
)
then
led_red_o
<=
'0'
;
end
if
;
if
(
sysc_regs_o
.
gpsr_led_stat_o
=
'1'
)
then
led_green_o
<=
'1'
;
elsif
(
sysc_regs_o
.
gpcr_led_stat_o
=
'1'
)
then
led_green_o
<=
'0'
;
end
if
;
end
if
;
end
process
;
-------------------------------------
-- buttons
-------------------------------------
...
...
modules/wrc_core/wrcore_pkg.vhd
View file @
8feb29dc
...
...
@@ -6,7 +6,6 @@
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-05-11
-- Last update: 2023-05-05
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
...
...
@@ -297,8 +296,6 @@ package wrcore_pkg is
rst_n_i
:
in
std_logic
;
rst_net_n_o
:
out
std_logic
;
rst_wrc_n_o
:
out
std_logic
;
led_red_o
:
out
std_logic
;
led_green_o
:
out
std_logic
;
scl_o
:
out
std_logic
;
scl_i
:
in
std_logic
;
sda_o
:
out
std_logic
;
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment