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White Rabbit core collection
Commit 092c4b9e authored by Peter Jansweijer's avatar Peter Jansweijer
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Generalize lpdc_mdio_regs aux_reset

parent 37c8eebd
Pipeline #4608 failed with stage
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    platform/xilinx/wr_gtp_phy/common/lpdc_mdio_regs.cheby
    View file @ 092c4b9e
    ......@@ -71,8 +71,8 @@ memory-map:
    description: Reset of PHY CPLL or QPLL
    range: 4
    - field:
    name: txusrpll_reset
    description: Reset of PHY TXUSRCLK PLL (GTXE1/2)
    name: aux_reset
    description: Auxiliary Reset of PHY (for example to reset TXUSRCLK PLL)
    range: 5
    - field:
    name: comma_target_pos
    ......
    platform/xilinx/wr_gtp_phy/common/lpdc_mdio_regs.vhd
    View file @ 092c4b9e
    -- Do not edit. Generated by cheby 1.6.dev0 using these options:
    -- -i lpdc_mdio_regs.cheby --gen-hdl lpdc_mdio_regs.vhd
    -- Generated on Wed Jun 07 15:24:40 2023 by peterj
    -- Generated on Wed Jun 07 15:26:27 2023 by peterj
    library ieee;
    ......@@ -15,7 +15,7 @@ package lpdc_mdio_regs_pkg is
    CTRL_rx_enable : std_logic;
    CTRL_rx_sw_reset : std_logic;
    CTRL_pll_sw_reset : std_logic;
    CTRL_txusrpll_reset : std_logic;
    CTRL_aux_reset : std_logic;
    CTRL_comma_target_pos : std_logic_vector(7 downto 0);
    CTRL_dmtd_clk_sel : std_logic_vector(1 downto 0);
    CTRL2_rx_rate : std_logic_vector(2 downto 0);
    ......@@ -91,7 +91,7 @@ architecture syn of lpdc_mdio_regs is
    signal CTRL_rx_enable_reg : std_logic;
    signal CTRL_rx_sw_reset_reg : std_logic;
    signal CTRL_pll_sw_reset_reg : std_logic;
    signal CTRL_txusrpll_reset_reg : std_logic;
    signal CTRL_aux_reset_reg : std_logic;
    signal CTRL_comma_target_pos_reg : std_logic_vector(7 downto 0);
    signal CTRL_dmtd_clk_sel_reg : std_logic_vector(1 downto 0);
    signal CTRL_wreq : std_logic;
    ......@@ -171,7 +171,7 @@ begin
    lpdc_regs_o.CTRL_rx_enable <= CTRL_rx_enable_reg;
    lpdc_regs_o.CTRL_rx_sw_reset <= CTRL_rx_sw_reset_reg;
    lpdc_regs_o.CTRL_pll_sw_reset <= CTRL_pll_sw_reset_reg;
    lpdc_regs_o.CTRL_txusrpll_reset <= CTRL_txusrpll_reset_reg;
    lpdc_regs_o.CTRL_aux_reset <= CTRL_aux_reset_reg;
    lpdc_regs_o.CTRL_comma_target_pos <= CTRL_comma_target_pos_reg;
    lpdc_regs_o.CTRL_dmtd_clk_sel <= CTRL_dmtd_clk_sel_reg;
    process (clk_i) begin
    ......@@ -182,7 +182,7 @@ begin
    CTRL_rx_enable_reg <= '0';
    CTRL_rx_sw_reset_reg <= '0';
    CTRL_pll_sw_reset_reg <= '0';
    CTRL_txusrpll_reset_reg <= '0';
    CTRL_aux_reset_reg <= '0';
    CTRL_comma_target_pos_reg <= "00000000";
    CTRL_dmtd_clk_sel_reg <= "00";
    CTRL_wack <= '0';
    ......@@ -193,7 +193,7 @@ begin
    CTRL_rx_enable_reg <= wr_dat_d0(2);
    CTRL_rx_sw_reset_reg <= wr_dat_d0(3);
    CTRL_pll_sw_reset_reg <= wr_dat_d0(4);
    CTRL_txusrpll_reset_reg <= wr_dat_d0(5);
    CTRL_aux_reset_reg <= wr_dat_d0(5);
    CTRL_comma_target_pos_reg <= wr_dat_d0(13 downto 6);
    CTRL_dmtd_clk_sel_reg <= wr_dat_d0(15 downto 14);
    end if;
    ......@@ -346,7 +346,7 @@ begin
    -- Process for read requests.
    process (adr_int, rd_req_int, CTRL_tx_sw_reset_reg, CTRL_tx_enable_reg,
    CTRL_rx_enable_reg, CTRL_rx_sw_reset_reg, CTRL_pll_sw_reset_reg,
    CTRL_txusrpll_reset_reg, CTRL_comma_target_pos_reg,
    CTRL_aux_reset_reg, CTRL_comma_target_pos_reg,
    CTRL_dmtd_clk_sel_reg, lpdc_regs_i.STAT_pll_locked,
    lpdc_regs_i.STAT_link_up, lpdc_regs_i.STAT_link_aligned,
    lpdc_regs_i.STAT_tx_rst_done, lpdc_regs_i.STAT_txusrpll_locked,
    ......@@ -375,7 +375,7 @@ begin
    rd_dat_d0(2) <= CTRL_rx_enable_reg;
    rd_dat_d0(3) <= CTRL_rx_sw_reset_reg;
    rd_dat_d0(4) <= CTRL_pll_sw_reset_reg;
    rd_dat_d0(5) <= CTRL_txusrpll_reset_reg;
    rd_dat_d0(5) <= CTRL_aux_reset_reg;
    rd_dat_d0(13 downto 6) <= CTRL_comma_target_pos_reg;
    rd_dat_d0(15 downto 14) <= CTRL_dmtd_clk_sel_reg;
    rd_dat_d0(31 downto 16) <= (others => '0');
    ......
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