dmtd_sampler: make oversamping enable signal truly sync

... with the input clock

dmtd_sampler: make oversamping enable signal truly sync
... with the input clock
2cc1bd74 · Tristan Gingold · cf7ae807 · 2cc1bd74
Commit 2cc1bd74 authored Sep 18, 2023 by Tristan Gingold
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dmtd_sampler.vhd modules/timing/dmtd_sampler.vhd +2 -2

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--- a/modules/timing/dmtd_sampler.vhd
+++ b/modules/timing/dmtd_sampler.vhd
@@ -175,10 +175,10 @@ begin  -- rtl
    p_the_dmtd_itself : process(clk_in)
    begin
      if rising_edge(clk_in) then
-        if en_i = '1' then
          clk_i_d0 <= clk_dmtd_i;
+        if en_i = '1' then
+          clk_i_d1 <= clk_i_d0;
        end if;
-        clk_i_d1 <= clk_i_d0;
      end if;
    end process;