wr_softpll_ng: improved CDC logic. Fixes rare no-locks/FIFO errors, likely due…

wr_softpll_ng: improved CDC logic. Fixes rare no-locks/FIFO errors, likely due to synthesizer doing some weird cross-clock-domains logic optimizations

wr_softpll_ng: improved CDC logic. Fixes rare no-locks/FIFO errors, likely due…
wr_softpll_ng: improved CDC logic. Fixes rare no-locks/FIFO errors, likely due to synthesizer doing some weird cross-clock-domains logic optimizations
89fd975c · Tomasz Wlostowski · ccd0d2d6 · 89fd975c · 89fd975c · 89fd975c
Commit 89fd975c authored Nov 06, 2023 by Tomasz Wlostowski
Showing with 65 additions and 13 deletions

dmtd_sampler.vhd modules/timing/dmtd_sampler.vhd +13 -9

dmtd_with_deglitcher.vhd modules/timing/dmtd_with_deglitcher.vhd +40 -3

wr_softpll_ng.vhd modules/wr_softpll_ng/wr_softpll_ng.vhd +12 -1

No files found.
--- a/modules/timing/dmtd_sampler.vhd
+++ b/modules/timing/dmtd_sampler.vhd
@@ -135,6 +135,8 @@ begin  -- rtl
      end if;
    end process;

+    clk_sampled_o <= clk_i_d3;
+
  end generate gen_straight_oversampled;


@@ -164,6 +166,9 @@ begin  -- rtl
      end if;
    end process;

+    clk_sampled_o <= clk_i_d3;
+
+
  end generate gen_straight_nonoversampled;

  gen_reverse_nonoversampled : if(g_reverse = true and g_with_oversampling = false) generate
@@ -182,17 +187,16 @@ begin  -- rtl
      end if;
    end process;

-    p_sync : process(clk_dmtd_i)
-    begin
-      if rising_edge(clk_dmtd_i) then
-        clk_i_dx <= clk_i_d1;
-        clk_i_d2 <= not clk_i_dx;
-        clk_i_d3 <= clk_i_d2;
-      end if;
-    end process;
+    inst_sync_1: entity work.gc_sync
+      port map (
+        clk_i     => clk_dmtd_i,
+        rst_n_a_i => '1',
+        d_i       => clk_i_d1,
+        q_o       => clk_i_d3);
+
+    clk_sampled_o <= not clk_i_d3;

  end generate gen_reverse_nonoversampled;

-  clk_sampled_o <= clk_i_d3;

 end rtl;
--- a/modules/timing/dmtd_with_deglitcher.vhd
+++ b/modules/timing/dmtd_with_deglitcher.vhd
@@ -167,6 +167,16 @@ architecture rtl of dmtd_with_deglitcher is
  signal stat_discard_p : std_logic;
  signal stat_ready_dmtd, r_minmax_reset_dmtd : std_logic;

+  attribute mark_debug : string;
+  attribute mark_debug of free_cntr : signal is "true";
+  attribute mark_debug of state : signal is "true";
+  attribute mark_debug of tag_o : signal is "true";
+  attribute mark_debug of tag_stb_p1_o : signal is "true";
+
+  signal tag_latched_dmtdclk : std_logic_vector(g_counter_bits-1 downto 0);
+  signal tag_latched_sysclk : std_logic_vector(g_counter_bits-1 downto 0);
+  signal new_edge_p_sysclk_d0 : std_logic;
+  
 begin  -- rtl

  U_Sync_Resync_Pulse : gc_sync_ffs
@@ -257,8 +267,8 @@ begin  -- rtl

            if stab_cntr = unsigned(r_deglitch_threshold_i) then
              state         <= WAIT_STABLE_0;
-              tag_o         <= std_logic_vector(tag_int);
              new_edge_p_dmtdclk <= '1';
+              tag_latched_dmtdclk <= std_logic_vector(tag_int);
              stab_cntr     <= (others => '0');
              stat_discard_p <= '1';
            elsif (clk_sampled = '0') then
@@ -366,6 +376,15 @@ begin  -- rtl
  end process;


+  U_sync_tag : entity work.gc_sync_register
+      generic map (
+        g_width => g_counter_bits)
+      port map (
+        clk_i     => clk_sys_i,
+        rst_n_a_i => rst_n_sysclk_i,
+        d_i       => tag_latched_dmtdclk,
+        q_o       => tag_latched_sysclk);
+  

  U_sync_tag_strobe : entity work.gc_pulse_synchronizer2
      port map (
@@ -376,8 +395,26 @@ begin  -- rtl
        d_p_i       => new_edge_p_dmtdclk,
        q_p_o       => new_edge_p_sysclk);

-  tag_stb_p1_o <= new_edge_p_sysclk;
-
+  p_tag_output : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_sysclk_i = '0' then
+        tag_stb_p1_o <= '0';
+      else
+        new_edge_p_sysclk_d0 <= new_edge_p_sysclk;
+        
+        if new_edge_p_sysclk_d0 = '1' then
+          tag_o <= tag_latched_sysclk;
+          tag_stb_p1_o <= '1';
+        else
+          tag_stb_p1_o <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  
+  
  U_Extend_Debug_Pulses : gc_extend_pulse
    generic map (
      g_width => 3000)

--- a/modules/wr_softpll_ng/wr_softpll_ng.vhd
+++ b/modules/wr_softpll_ng/wr_softpll_ng.vhd
@@ -79,7 +79,7 @@ entity wr_softpll_ng is
 -- use with care.
    g_divide_input_by_2 : boolean := false;

-    g_with_jitter_stats_regs : boolean := true;
+    g_with_jitter_stats_regs : boolean := false;
    
    g_ref_clock_rate : integer := 125_000_000;
    g_ext_clock_rate : integer :=  10_000_000;
@@ -323,6 +323,14 @@ architecture rtl of wr_softpll_ng is
  signal r_stat_high_fb : t_stat_array(0 to g_num_outputs-1);
  signal r_stat_low_fb : t_stat_array(0 to g_num_outputs-1);
  signal r_stat_valid_fb : std_logic_vector(g_num_outputs-1 downto 0);
+
+  signal trr_wr_full : std_logic;
+
+  attribute mark_debug : string;
+  attribute mark_debug of tag_muxed : signal is "true";
+  attribute mark_debug of trr_wr_full : signal is "true";
+  attribute mark_debug of tag_valid : signal is "true";
+  
  
    
 begin  -- rtl
@@ -706,6 +714,9 @@ begin  -- rtl
    end if;
  end process;

+
+  trr_wr_full <= regs_in.trr_wr_full_o;
+
  regs_out.trr_wr_req_i  <= tag_valid and not regs_in.trr_wr_full_o;
  regs_out.trr_chan_id_i <= '0'&tag_src;