boards: fix incorrect logic of reset input for aasd

The arst_i input of gc_reset_multi_aasd is active high, so the resets must be or-ed (using positive logic)

boards: fix incorrect logic of reset input for aasd
The arst_i input of gc_reset_multi_aasd is active high, so the resets must be or-ed (using positive logic)
2d7e0245 · Tristan Gingold · 1ee142a3 · 2d7e0245 · 2d7e0245 · 2d7e0245
Commit 2d7e0245 authored Jul 20, 2023 by Tristan Gingold
4 changed files
--- a/board/diot-sb/wrc_board_diot_simple.vhd
+++ b/board/diot-sb/wrc_board_diot_simple.vhd
@@ -225,8 +225,8 @@ begin
  --    data_i   => areset_edge_n_i,
  --    ppulse_o => areset_edge_ppulse);

-  -- logic AND of all async reset sources (active high)
-  rstlogic_arst <= (not pll_locked) and (not areset_n_i);
+  -- logic OR of all async reset sources (active high)
+  rstlogic_arst <= (not pll_locked) or (not areset_n_i);

  -- concatenation of all clocks required to have synced resets
  rstlogic_clk_in(0)          <= clk_pll_62m5;

--- a/board/pxie-fmc/xwrc_board_pxie_fmc.vhd
+++ b/board/pxie-fmc/xwrc_board_pxie_fmc.vhd
@@ -322,8 +322,8 @@ begin  -- architecture struct
      data_i   => areset_edge_n_i,
      ppulse_o => areset_edge_ppulse);

-  -- logic AND of all async reset sources (active high)
-  rstlogic_arst <= (not pll_locked) and (not areset_n_i) and areset_edge_ppulse;
+  -- logic OR of all async reset sources (active high)
+  rstlogic_arst <= (not pll_locked) or (not areset_n_i) or areset_edge_ppulse;

  -- concatenation of all clocks required to have synced resets
  rstlogic_clk_in(0)          <= clk_pll_62m5;

--- a/board/spec/xwrc_board_spec.vhd
+++ b/board/spec/xwrc_board_spec.vhd
@@ -7,7 +7,6 @@
 -- Author(s)  : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Created    : 2017-02-17
-- Last update: 2022-03-10
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
 -- Description: Top-level wrapper for WR PTP core including all the modules
@@ -387,7 +386,7 @@ begin  -- architecture struct
      data_i   => areset_edge_n_i,
      ppulse_o => areset_edge_ppulse);

-  -- logic AND of all async reset sources (active high)
+  -- logic OR of all async reset sources (active high)
  rstlogic_arst <= (not pll_locked) or (not areset_n_i) or areset_edge_ppulse;

  -- concatenation of all clocks required to have synced resets

--- a/board/svec/xwrc_board_svec.vhd
+++ b/board/svec/xwrc_board_svec.vhd
@@ -7,7 +7,6 @@
 -- Author(s)  : Dimitrios Lampridis  <dimitrios.lampridis@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Created    : 2017-02-16
-- Last update: 2022-03-10
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
 -- Description: Top-level wrapper for WR PTP core including all the modules
@@ -383,8 +382,8 @@ begin  -- architecture struct
      data_i   => areset_edge_n_i,
      ppulse_o => areset_edge_ppulse);

-  -- logic AND of all async reset sources (active high)
-  rstlogic_arst <= (not pll_locked) and (not areset_n_i) and areset_edge_ppulse;
+  -- logic OR of all async reset sources (active high)
+  rstlogic_arst <= (not pll_locked) or (not areset_n_i) or areset_edge_ppulse;

  -- concatenation of all clocks required to have synced resets
  rstlogic_clk_in(0)          <= clk_pll_62m5;