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Commit a27f660b authored by Tristan Gingold's avatar Tristan Gingold
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Merge branch 'peter_lpdc_mdio_regs_generalize' into 'wrpc-v5' 

Peter lpdc mdio regs generalize

See merge request !7
parents 7be4a6d7 092c4b9e
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    platform/xilinx/wr_gtp_phy/common/lpdc_mdio_regs.cheby
    View file @ a27f660b
    ......@@ -67,12 +67,12 @@ memory-map:
    description: Reset of PHY RX path
    range: 3
    - field:
    name: qpll_sw_reset
    description: Reset of PHY QPLL (GTXE1/2)
    name: pll_sw_reset
    description: Reset of PHY CPLL or QPLL
    range: 4
    - field:
    name: txusrpll_reset
    description: Reset of PHY TXUSRCLK PLL (GTXE1/2)
    name: aux_reset
    description: Auxiliary Reset of PHY (for example to reset TXUSRCLK PLL)
    range: 5
    - field:
    name: comma_target_pos
    ......@@ -91,8 +91,8 @@ memory-map:
    address: 0x4
    children:
    - field:
    name: qpll_locked
    description: QPLL lock indication
    name: pll_locked
    description: CPLL or QPLL lock indication
    range: 0
    - field:
    name: link_up
    ......
    platform/xilinx/wr_gtp_phy/common/lpdc_mdio_regs.vhd
    View file @ a27f660b
    -- Do not edit. Generated by cheby 1.5.dev0 using these options:
    -- Do not edit. Generated by cheby 1.6.dev0 using these options:
    -- -i lpdc_mdio_regs.cheby --gen-hdl lpdc_mdio_regs.vhd
    -- Generated on Fri May 19 22:58:01 2023 by twl
    -- Generated on Wed Jun 07 15:26:27 2023 by peterj
    library ieee;
    ......@@ -14,8 +14,8 @@ package lpdc_mdio_regs_pkg is
    CTRL_tx_enable : std_logic;
    CTRL_rx_enable : std_logic;
    CTRL_rx_sw_reset : std_logic;
    CTRL_qpll_sw_reset : std_logic;
    CTRL_txusrpll_reset : std_logic;
    CTRL_pll_sw_reset : std_logic;
    CTRL_aux_reset : std_logic;
    CTRL_comma_target_pos : std_logic_vector(7 downto 0);
    CTRL_dmtd_clk_sel : std_logic_vector(1 downto 0);
    CTRL2_rx_rate : std_logic_vector(2 downto 0);
    ......@@ -27,7 +27,7 @@ package lpdc_mdio_regs_pkg is
    subtype t_lpdc_regs_slave_in is t_lpdc_regs_master_out;
    type t_lpdc_regs_slave_out is record
    STAT_qpll_locked : std_logic;
    STAT_pll_locked : std_logic;
    STAT_link_up : std_logic;
    STAT_link_aligned : std_logic;
    STAT_tx_rst_done : std_logic;
    ......@@ -90,8 +90,8 @@ architecture syn of lpdc_mdio_regs is
    signal CTRL_tx_enable_reg : std_logic;
    signal CTRL_rx_enable_reg : std_logic;
    signal CTRL_rx_sw_reset_reg : std_logic;
    signal CTRL_qpll_sw_reset_reg : std_logic;
    signal CTRL_txusrpll_reset_reg : std_logic;
    signal CTRL_pll_sw_reset_reg : std_logic;
    signal CTRL_aux_reset_reg : std_logic;
    signal CTRL_comma_target_pos_reg : std_logic_vector(7 downto 0);
    signal CTRL_dmtd_clk_sel_reg : std_logic_vector(1 downto 0);
    signal CTRL_wreq : std_logic;
    ......@@ -170,8 +170,8 @@ begin
    lpdc_regs_o.CTRL_tx_enable <= CTRL_tx_enable_reg;
    lpdc_regs_o.CTRL_rx_enable <= CTRL_rx_enable_reg;
    lpdc_regs_o.CTRL_rx_sw_reset <= CTRL_rx_sw_reset_reg;
    lpdc_regs_o.CTRL_qpll_sw_reset <= CTRL_qpll_sw_reset_reg;
    lpdc_regs_o.CTRL_txusrpll_reset <= CTRL_txusrpll_reset_reg;
    lpdc_regs_o.CTRL_pll_sw_reset <= CTRL_pll_sw_reset_reg;
    lpdc_regs_o.CTRL_aux_reset <= CTRL_aux_reset_reg;
    lpdc_regs_o.CTRL_comma_target_pos <= CTRL_comma_target_pos_reg;
    lpdc_regs_o.CTRL_dmtd_clk_sel <= CTRL_dmtd_clk_sel_reg;
    process (clk_i) begin
    ......@@ -181,8 +181,8 @@ begin
    CTRL_tx_enable_reg <= '0';
    CTRL_rx_enable_reg <= '0';
    CTRL_rx_sw_reset_reg <= '0';
    CTRL_qpll_sw_reset_reg <= '0';
    CTRL_txusrpll_reset_reg <= '0';
    CTRL_pll_sw_reset_reg <= '0';
    CTRL_aux_reset_reg <= '0';
    CTRL_comma_target_pos_reg <= "00000000";
    CTRL_dmtd_clk_sel_reg <= "00";
    CTRL_wack <= '0';
    ......@@ -192,8 +192,8 @@ begin
    CTRL_tx_enable_reg <= wr_dat_d0(1);
    CTRL_rx_enable_reg <= wr_dat_d0(2);
    CTRL_rx_sw_reset_reg <= wr_dat_d0(3);
    CTRL_qpll_sw_reset_reg <= wr_dat_d0(4);
    CTRL_txusrpll_reset_reg <= wr_dat_d0(5);
    CTRL_pll_sw_reset_reg <= wr_dat_d0(4);
    CTRL_aux_reset_reg <= wr_dat_d0(5);
    CTRL_comma_target_pos_reg <= wr_dat_d0(13 downto 6);
    CTRL_dmtd_clk_sel_reg <= wr_dat_d0(15 downto 14);
    end if;
    ......@@ -345,9 +345,9 @@ begin
    -- Process for read requests.
    process (adr_int, rd_req_int, CTRL_tx_sw_reset_reg, CTRL_tx_enable_reg,
    CTRL_rx_enable_reg, CTRL_rx_sw_reset_reg, CTRL_qpll_sw_reset_reg,
    CTRL_txusrpll_reset_reg, CTRL_comma_target_pos_reg,
    CTRL_dmtd_clk_sel_reg, lpdc_regs_i.STAT_qpll_locked,
    CTRL_rx_enable_reg, CTRL_rx_sw_reset_reg, CTRL_pll_sw_reset_reg,
    CTRL_aux_reset_reg, CTRL_comma_target_pos_reg,
    CTRL_dmtd_clk_sel_reg, lpdc_regs_i.STAT_pll_locked,
    lpdc_regs_i.STAT_link_up, lpdc_regs_i.STAT_link_aligned,
    lpdc_regs_i.STAT_tx_rst_done, lpdc_regs_i.STAT_txusrpll_locked,
    lpdc_regs_i.STAT_rx_rst_done, lpdc_regs_i.STAT_comma_current_pos,
    ......@@ -374,15 +374,15 @@ begin
    rd_dat_d0(1) <= CTRL_tx_enable_reg;
    rd_dat_d0(2) <= CTRL_rx_enable_reg;
    rd_dat_d0(3) <= CTRL_rx_sw_reset_reg;
    rd_dat_d0(4) <= CTRL_qpll_sw_reset_reg;
    rd_dat_d0(5) <= CTRL_txusrpll_reset_reg;
    rd_dat_d0(4) <= CTRL_pll_sw_reset_reg;
    rd_dat_d0(5) <= CTRL_aux_reset_reg;
    rd_dat_d0(13 downto 6) <= CTRL_comma_target_pos_reg;
    rd_dat_d0(15 downto 14) <= CTRL_dmtd_clk_sel_reg;
    rd_dat_d0(31 downto 16) <= (others => '0');
    when "0000000001" =>
    -- Reg STAT
    rd_ack_d0 <= rd_req_int;
    rd_dat_d0(0) <= lpdc_regs_i.STAT_qpll_locked;
    rd_dat_d0(0) <= lpdc_regs_i.STAT_pll_locked;
    rd_dat_d0(1) <= lpdc_regs_i.STAT_link_up;
    rd_dat_d0(2) <= lpdc_regs_i.STAT_link_aligned;
    rd_dat_d0(3) <= lpdc_regs_i.STAT_tx_rst_done;
    ......
    platform/xilinx/wr_gtp_phy/kintex7-lp/wr_gtx_phy_kintex7_lp.vhd
    View file @ a27f660b
    ......@@ -332,7 +332,7 @@ begin -- rtl
    (
    clk_i => clk_dmtd_i,
    rst_n_i => '1',
    data_i => lpdc_regs_out.CTRL_qpll_sw_reset,
    data_i => lpdc_regs_out.CTRL_pll_sw_reset,
    synced_o => cpll_reset
    );
    ......@@ -786,7 +786,7 @@ begin -- rtl
    clk_i => clk_sys_i,
    rst_n_i => rst_sys_n_i,
    data_i => cpll_locked,
    synced_o => lpdc_regs_in.STAT_qpll_locked
    synced_o => lpdc_regs_in.STAT_pll_locked
    );
    inst_sync_rx_pll_locked : gc_sync_ffs
    ......
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