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White Rabbit core collection
Commits
4fe0f3cc
Commit
4fe0f3cc
authored
Jul 16, 2023
by
Tomasz Wlostowski
Committed by
Tristan Gingold
Sep 06, 2023
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wr_softpll_ng: extend DAC bit count in DAC_HELPER/DAC_MAIN regs to 24 for HW dithering
parent
4cc5b6f1
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6 changed files
with
34 additions
and
25 deletions
+34
-25
build_wb.sh
modules/wr_softpll_ng/build_wb.sh
+1
-1
spll_wb_slave.vhd
modules/wr_softpll_ng/spll_wb_slave.vhd
+4
-4
spll_wb_slave.wb
modules/wr_softpll_ng/spll_wb_slave.wb
+2
-2
spll_wbgen2_pkg.vhd
modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
+3
-3
wr_softpll_ng.vhd
modules/wr_softpll_ng/wr_softpll_ng.vhd
+5
-2
softpll_regs_ng.vh
sim/softpll_regs_ng.vh
+19
-13
No files found.
modules/wr_softpll_ng/build_wb.sh
View file @
4fe0f3cc
#!/bin/bash
wbgen2
-D
./doc/softpll.html
-C
softpll_regs.h
-V
spll_wb_slave.vhd
-K
../../sim/softpll_regs_ng.vh
-C
softpll_regs.h
--hstyle
record
-p
spll_wbgen2_pkg.vhd spll_wb_slave.wb
wbgen2
-D
./doc/softpll.html
-C
softpll_regs.h
-V
spll_wb_slave.vhd
-K
../../sim/softpll_regs_ng.vh
-C
softpll_regs.h
--hstyle
record
-
-cstyle
struct
-
p
spll_wbgen2_pkg.vhd spll_wb_slave.wb
modules/wr_softpll_ng/spll_wb_slave.vhd
View file @
4fe0f3cc
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : spll_wb_slave.vhd
-- Author : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created :
Thu Jul 6 13:28:58
2023
-- Created :
Sun Jul 16 23:36:22
2023
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
...
...
@@ -814,13 +814,13 @@ regs_o.rcer_o <= wrdata_reg(31 downto 0);
regs_o
.
ocer_o
<=
wrdata_reg
(
7
downto
0
);
-- DAC value
-- pass-through field: DAC value in register: Helper DAC Output
regs_o
.
dac_hpll_o
<=
wrdata_reg
(
15
downto
0
);
regs_o
.
dac_hpll_o
<=
wrdata_reg
(
23
downto
0
);
-- DAC value
-- pass-through field: DAC value in register: Main DAC Output
regs_o
.
dac_main_value_o
<=
wrdata_reg
(
15
downto
0
);
regs_o
.
dac_main_value_o
<=
wrdata_reg
(
23
downto
0
);
-- DAC select
-- pass-through field: DAC select in register: Main DAC Output
regs_o
.
dac_main_dac_sel_o
<=
wrdata_reg
(
19
downto
16
);
regs_o
.
dac_main_dac_sel_o
<=
wrdata_reg
(
27
downto
24
);
-- Threshold
regs_o
.
deglitch_thr_o
<=
spll_deglitch_thr_int
;
-- Debug Value
...
...
modules/wr_softpll_ng/spll_wb_slave.wb
View file @
4fe0f3cc
...
...
@@ -307,7 +307,7 @@ peripheral {
field {
name = "DAC value";
type = PASS_THROUGH;
size =
16
;
size =
24
;
};
};
...
...
@@ -319,7 +319,7 @@ peripheral {
name = "DAC value";
prefix = "VALUE";
type = PASS_THROUGH;
size =
16
;
size =
24
;
};
field {
...
...
modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
View file @
4fe0f3cc
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : spll_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created :
Thu Jul 6 13:28:58
2023
-- Created :
Sun Jul 16 23:36:22
2023
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
...
...
@@ -94,9 +94,9 @@ package spll_wbgen2_pkg is
rcer_load_o
:
std_logic
;
ocer_o
:
std_logic_vector
(
7
downto
0
);
ocer_load_o
:
std_logic
;
dac_hpll_o
:
std_logic_vector
(
15
downto
0
);
dac_hpll_o
:
std_logic_vector
(
23
downto
0
);
dac_hpll_wr_o
:
std_logic
;
dac_main_value_o
:
std_logic_vector
(
15
downto
0
);
dac_main_value_o
:
std_logic_vector
(
23
downto
0
);
dac_main_value_wr_o
:
std_logic
;
dac_main_dac_sel_o
:
std_logic_vector
(
3
downto
0
);
dac_main_dac_sel_wr_o
:
std_logic
;
...
...
modules/wr_softpll_ng/wr_softpll_ng.vhd
View file @
4fe0f3cc
...
...
@@ -383,6 +383,8 @@ begin -- rtl
r_stat_reset_i
=>
regs_in
.
dmtd_stat_cr_rst_o
,
r_stat_ready_o
=>
r_stat_valid_ref
(
i
)
);
end
generate
gen_ref_dmtds
;
gen_feedback_dmtds
:
for
i
in
0
to
g_num_outputs
-1
generate
...
...
@@ -456,6 +458,7 @@ begin -- rtl
tag_stb_p1_o
=>
tags_p
(
g_num_ref_inputs
+
g_num_outputs
+
I
),
r_deglitch_threshold_i
=>
deglitch_thr_slv
);
end
generate
gen_ext_dmtds
;
gen_with_ext_clock_input
:
if
g_num_exts
>
0
generate
...
...
@@ -790,9 +793,9 @@ begin -- rtl
regs_out
.
csr_n_out_i
<=
std_logic_vector
(
to_unsigned
(
g_num_outputs
,
regs_out
.
csr_n_out_i
'length
));
dac_dmtd_load_o
<=
regs_in
.
dac_hpll_wr_o
;
dac_dmtd_data_o
<=
regs_in
.
dac_hpll_o
;
dac_dmtd_data_o
<=
regs_in
.
dac_hpll_o
(
g_dac_bits
-1
downto
0
)
;
dac_out_data_o
<=
regs_in
.
dac_main_value_o
;
dac_out_data_o
<=
regs_in
.
dac_main_value_o
(
g_dac_bits
-1
downto
0
)
;
dac_out_sel_o
<=
regs_in
.
dac_main_dac_sel_o
;
dac_out_load_o
<=
regs_in
.
dac_main_value_wr_o
;
...
...
sim/softpll_regs_ng.vh
View file @
4fe0f3cc
...
...
@@ -25,16 +25,22 @@
`define SPLL_AL_CR_REQUIRED 32'h0003fe00
`define ADDR_SPLL_AL_CREF 8'hc
`define ADDR_SPLL_AL_CIN 8'h10
`define ADDR_SPLL_F_DMTD 8'h14
`define SPLL_F_DMTD_FREQ_OFFSET 0
`define SPLL_F_DMTD_FREQ 32'h0fffffff
`define SPLL_F_DMTD_VALID_OFFSET 28
`define SPLL_F_DMTD_VALID 32'h10000000
`define ADDR_SPLL_F_REF 8'h18
`define SPLL_F_REF_FREQ_OFFSET 0
`define SPLL_F_REF_FREQ 32'h0fffffff
`define SPLL_F_REF_VALID_OFFSET 28
`define SPLL_F_REF_VALID 32'h10000000
`define ADDR_SPLL_DMTD_STAT_CR 8'h14
`define SPLL_DMTD_STAT_CR_SAMPLES_OFFSET 0
`define SPLL_DMTD_STAT_CR_SAMPLES 32'h0000ffff
`define SPLL_DMTD_STAT_CR_VALID_OFFSET 16
`define SPLL_DMTD_STAT_CR_VALID 32'h00010000
`define SPLL_DMTD_STAT_CR_RST_OFFSET 17
`define SPLL_DMTD_STAT_CR_RST 32'h00020000
`define SPLL_DMTD_STAT_CR_MINMAX_SEL_OFFSET 18
`define SPLL_DMTD_STAT_CR_MINMAX_SEL 32'h00040000
`define SPLL_DMTD_STAT_CR_CHAN_SEL_OFFSET 19
`define SPLL_DMTD_STAT_CR_CHAN_SEL 32'h00780000
`define ADDR_SPLL_DMTD_STAT_VAL 8'h18
`define SPLL_DMTD_STAT_VAL_HIGH_OFFSET 0
`define SPLL_DMTD_STAT_VAL_HIGH 32'h0000ffff
`define SPLL_DMTD_STAT_VAL_LOW_OFFSET 16
`define SPLL_DMTD_STAT_VAL_LOW 32'hffff0000
`define ADDR_SPLL_F_EXT 8'h1c
`define SPLL_F_EXT_FREQ_OFFSET 0
`define SPLL_F_EXT_FREQ 32'h0fffffff
...
...
@@ -50,9 +56,9 @@
`define ADDR_SPLL_DAC_HPLL 8'h40
`define ADDR_SPLL_DAC_MAIN 8'h44
`define SPLL_DAC_MAIN_VALUE_OFFSET 0
`define SPLL_DAC_MAIN_VALUE 32'h00
00
ffff
`define SPLL_DAC_MAIN_DAC_SEL_OFFSET
16
`define SPLL_DAC_MAIN_DAC_SEL 32'h0
00f
0000
`define SPLL_DAC_MAIN_VALUE 32'h00
ff
ffff
`define SPLL_DAC_MAIN_DAC_SEL_OFFSET
24
`define SPLL_DAC_MAIN_DAC_SEL 32'h0
f00
0000
`define ADDR_SPLL_DEGLITCH_THR 8'h48
`define ADDR_SPLL_DFR_SPLL 8'h4c
`define SPLL_DFR_SPLL_VALUE_OFFSET 0
...
...
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