dmtd_with_deglitcher: add optional jitter measurement

4cc5b6f1 · Tristan Gingold · a224e333 · 4cc5b6f1 · 4cc5b6f1 · 4cc5b6f1
Commit 4cc5b6f1 authored Sep 06, 2023 by Tristan Gingold
5 changed files
--- a/modules/timing/dmtd_with_deglitcher.vhd
+++ b/modules/timing/dmtd_with_deglitcher.vhd
@@ -103,7 +103,6 @@ entity dmtd_with_deglitcher is

    -- [clk_dmtd_over_i] counter resync input (oversampled mode)
    resync_p_over_i : in std_logic := '0';
-
    -- CONTROL REGISTERS (wired from SoftPLL)

    -- [clk_dmtd_i] deglitcher threshold
@@ -114,6 +113,19 @@ entity dmtd_with_deglitcher is
    -- fractional mode PPS alignment clock divider
    r_oversample_pps_div_i : in std_logic_vector(5 downto 0) := (others => '0');

+    -- min/max stable 0 duration (selectable with r_minmax_sel_i)
+    r_low_o : out std_logic_vector(15 downto 0);
+    -- min/max stable 1 duration (selectable with r_minmax_sel_i)
+    r_high_o : out std_logic_vector(15 downto 0);
+    -- min/max sample count
+    r_samples_i : in std_logic_vector(15 downto 0) := (others => '0');
+    -- 1: calculate max low/high period, 0: calculate min low/high period.
+    r_minmax_sel_i : in std_logic := '0';
+    -- 1: resets r_low_o/r_high_o/r_samples_o
+    r_stat_reset_i : in std_logic := '0';
+
+    r_stat_ready_o : out std_logic;
+
    -- [clk_dmtd_i] raw DDMTD output (for debugging purposes)
    dbg_dmtdout_o : out std_logic;

@@ -122,7 +134,6 @@ entity dmtd_with_deglitcher is

    -- [clk_sys_i] deglitched edge tag value
    tag_o : out std_logic_vector(g_counter_bits-1 downto 0);
-    tag_pps_mark_o : out std_logic;

    -- [clk_sys_i] pulse indicates new phase tag on tag_o
    tag_stb_p1_o : out std_logic;
@@ -140,7 +151,8 @@ architecture rtl of dmtd_with_deglitcher is
  signal stab_cntr : unsigned(15 downto 0);
  signal free_cntr : unsigned(g_counter_bits-1 downto 0);

-  signal clk_sampled : std_logic;
+
+  signal clk_sampled, clk_sampled_d : std_logic;

  signal new_edge_sreg : std_logic_vector(5 downto 0);
  signal new_edge_p    : std_logic;
@@ -148,6 +160,12 @@ architecture rtl of dmtd_with_deglitcher is
  signal tag_int       : unsigned(g_counter_bits-1 downto 0);
  signal resync_p_dmtd : std_logic;

+  signal stat_sample_cnt : unsigned(15 downto 0);
+  signal stat_length_low, stat_length_high : unsigned(15 downto 0);
+  signal stat_length_low_minmax, stat_length_high_minmax : unsigned(15 downto 0);
+  signal stat_discard_cnt : unsigned(1 downto 0);
+  signal stat_discard_p : std_logic;
+  signal stat_ready_dmtd, r_minmax_reset_dmtd : std_logic;

 begin  -- rtl

@@ -182,6 +200,8 @@ begin  -- rtl
    clk_sampled <= clk_sampled_a_i;
  end generate gen_externally_sampled;

+
+
 -- glitchproof DMTD output edge detection
  p_deglitch : process (clk_dmtd_i)
  begin  -- process deglitch
@@ -193,12 +213,14 @@ begin  -- rtl
        state         <= WAIT_STABLE_0;
        free_cntr     <= (others => '0');
        new_edge_sreg <= (others => '0');
+        stat_discard_p <= '0';
      else
        free_cntr <= free_cntr + 1;

        case state is
          when WAIT_STABLE_0 =>         -- out-of-sync
            new_edge_sreg <= '0' & new_edge_sreg(new_edge_sreg'length-1 downto 1);
+            stat_discard_p <= '0';

            if clk_sampled /= '0' then
              stab_cntr <= (others => '0');
@@ -228,18 +250,100 @@ begin  -- rtl
              tag_o         <= std_logic_vector(tag_int);
              new_edge_sreg <= (others => '1');
              stab_cntr     <= (others => '0');
+              stat_discard_p <= '1';
            elsif (clk_sampled = '0') then
              stab_cntr <= (others => '0');
            else
              stab_cntr <= stab_cntr + 1;
            end if;
-
-
        end case;
      end if;
    end if;
  end process p_deglitch;

+
+  gen_with_jitter_stats : if g_with_jitter_stats_regs generate
+
+    inst_sync_stat_ready : gc_sync_ffs
+      generic map (
+        g_sync_edge => "positive")
+      port map (
+        clk_i    => clk_sys_i,
+        rst_n_i  => rst_n_sysclk_i,
+        data_i   => stat_ready_dmtd,
+        synced_o => r_stat_ready_o);
+
+    inst_sync_stat_reset : gc_sync_ffs
+      generic map (
+        g_sync_edge => "positive")
+      port map (
+        clk_i    => clk_dmtd_i,
+        rst_n_i  => rst_n_dmtdclk_i,
+        data_i   => r_stat_reset_i,
+        synced_o => r_minmax_reset_dmtd);
+
+    p_stats : process(clk_dmtd_i)
+    begin
+      if rising_edge(clk_dmtd_i) then
+        if r_minmax_reset_dmtd = '1' or rst_n_dmtdclk_i = '0' then
+          if r_minmax_sel_i = '1' then
+            -- max
+            stat_length_high_minmax <= (others => '0');
+            stat_length_low_minmax <= (others => '0');
+          else
+            -- min
+            stat_length_high_minmax <= (others => '1');
+            stat_length_low_minmax <= (others => '1');
+          end if;
+
+          stat_sample_cnt <= (others => '0');
+          stat_length_low <= (others => '0');
+          stat_length_high <= (others => '0');
+          stat_discard_cnt <= (others => '0');
+          stat_ready_dmtd <= '0';
+        else
+          if stat_sample_cnt = unsigned(r_samples_i) then
+            r_low_o <= std_logic_vector( stat_length_low_minmax );
+            r_high_o <= std_logic_vector( stat_length_high_minmax );
+            stat_ready_dmtd <= '1';
+          end if;
+
+          if stat_discard_p = '1' and stat_discard_cnt /= 3 then
+            stat_discard_cnt <= stat_discard_cnt + 1;
+          end if;
+
+          if stat_discard_cnt = 3 then
+            if clk_sampled = '1' then
+              stat_length_high <= stat_length_high + 1;
+              stat_length_low <= (others => '0');
+              if stat_length_low > unsigned(r_deglitch_threshold_i) then
+                stat_sample_cnt <= stat_sample_cnt + 1;
+                if r_minmax_sel_i = '0' and stat_length_low < stat_length_low_minmax then
+                  stat_length_low_minmax <= stat_length_low;
+                elsif r_minmax_sel_i = '1' and stat_length_low > stat_length_low_minmax then
+                  stat_length_low_minmax <= stat_length_low;
+                end if;
+              end if;
+            else
+              stat_length_low <= stat_length_low + 1;
+              stat_length_high <= (others => '0');
+
+              if stat_length_high > unsigned(r_deglitch_threshold_i) then
+                stat_sample_cnt <= stat_sample_cnt + 1;
+
+                if r_minmax_sel_i = '0' and stat_length_high < stat_length_high_minmax then
+                  stat_length_high_minmax <= stat_length_high;
+                elsif r_minmax_sel_i = '1' and stat_length_high > stat_length_low_minmax then
+                  stat_length_high_minmax <= stat_length_low;
+                end if;
+              end if;
+            end if;
+          end if;
+        end if;
+      end if;
+    end process;
+  end generate gen_with_jitter_stats;
+
  p_resync_pulse_output : process(clk_dmtd_i)
  begin
    if rising_edge(clk_dmtd_i) then

--- a/modules/wr_softpll_ng/spll_wb_slave.vhd
+++ b/modules/wr_softpll_ng/spll_wb_slave.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : spll_wb_slave.vhd
 -- Author         : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created        : Mon Apr  3 11:13:32 2023
+-- Created        : Thu Jul  6 13:28:58 2023
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
@@ -46,6 +46,11 @@ architecture syn of spll_wb_slave is

 signal spll_eccr_ext_en_int                     : std_logic      ;
 signal spll_eccr_ext_ref_pllrst_int             : std_logic      ;
+signal spll_dmtd_stat_cr_samples_int            : std_logic_vector(15 downto 0);
+signal spll_dmtd_stat_cr_rst_dly0               : std_logic      ;
+signal spll_dmtd_stat_cr_rst_int                : std_logic      ;
+signal spll_dmtd_stat_cr_minmax_sel_int         : std_logic      ;
+signal spll_dmtd_stat_cr_chan_sel_int           : std_logic_vector(3 downto 0);
 signal spll_occr_out_lock_int                   : std_logic_vector(7 downto 0);
 signal spll_deglitch_thr_int                    : std_logic_vector(15 downto 0);
 signal spll_dfr_host_rst_n                      : std_logic      ;
@@ -97,8 +102,10 @@ begin
    spll_eccr_ext_en_int <= '0';
    spll_eccr_ext_ref_pllrst_int <= '0';
    regs_o.al_cr_valid_load_o <= '0';
-    regs_o.f_dmtd_valid_load_o <= '0';
-    regs_o.f_ref_valid_load_o <= '0';
+    spll_dmtd_stat_cr_samples_int <= "0000000000000000";
+    spll_dmtd_stat_cr_rst_int <= '0';
+    spll_dmtd_stat_cr_minmax_sel_int <= '0';
+    spll_dmtd_stat_cr_chan_sel_int <= "0000";
    regs_o.f_ext_valid_load_o <= '0';
    spll_occr_out_lock_int <= "00000000";
    regs_o.rcer_load_o <= '0';
@@ -121,8 +128,7 @@ begin
    if (ack_in_progress = '1') then
      if (ack_sreg(0) = '1') then
        regs_o.al_cr_valid_load_o <= '0';
-        regs_o.f_dmtd_valid_load_o <= '0';
-        regs_o.f_ref_valid_load_o <= '0';
+        spll_dmtd_stat_cr_rst_int <= '0';
        regs_o.f_ext_valid_load_o <= '0';
        regs_o.rcer_load_o <= '0';
        regs_o.ocer_load_o <= '0';
@@ -137,8 +143,6 @@ begin
        ack_in_progress <= '0';
      else
        regs_o.al_cr_valid_load_o <= '0';
-        regs_o.f_dmtd_valid_load_o <= '0';
-        regs_o.f_ref_valid_load_o <= '0';
        regs_o.f_ext_valid_load_o <= '0';
        regs_o.rcer_load_o <= '0';
        regs_o.ocer_load_o <= '0';
@@ -251,24 +255,32 @@ begin
          ack_in_progress <= '1';
        when "000101" => 
          if (wb_we_i = '1') then
-            regs_o.f_dmtd_valid_load_o <= '1';
+            spll_dmtd_stat_cr_samples_int <= wrdata_reg(15 downto 0);
+            spll_dmtd_stat_cr_rst_int <= wrdata_reg(17);
+            spll_dmtd_stat_cr_minmax_sel_int <= wrdata_reg(18);
+            spll_dmtd_stat_cr_chan_sel_int <= wrdata_reg(22 downto 19);
          end if;
-          rddata_reg(27 downto 0) <= regs_i.f_dmtd_freq_i;
-          rddata_reg(28) <= regs_i.f_dmtd_valid_i;
+          rddata_reg(15 downto 0) <= spll_dmtd_stat_cr_samples_int;
+          rddata_reg(16) <= regs_i.dmtd_stat_cr_valid_i;
+          rddata_reg(17) <= '0';
+          rddata_reg(18) <= spll_dmtd_stat_cr_minmax_sel_int;
+          rddata_reg(22 downto 19) <= spll_dmtd_stat_cr_chan_sel_int;
+          rddata_reg(23) <= 'X';
+          rddata_reg(24) <= 'X';
+          rddata_reg(25) <= 'X';
+          rddata_reg(26) <= 'X';
+          rddata_reg(27) <= 'X';
+          rddata_reg(28) <= 'X';
          rddata_reg(29) <= 'X';
          rddata_reg(30) <= 'X';
          rddata_reg(31) <= 'X';
-          ack_sreg(0) <= '1';
+          ack_sreg(2) <= '1';
          ack_in_progress <= '1';
        when "000110" => 
          if (wb_we_i = '1') then
-            regs_o.f_ref_valid_load_o <= '1';
          end if;
-          rddata_reg(27 downto 0) <= regs_i.f_ref_freq_i;
-          rddata_reg(28) <= regs_i.f_ref_valid_i;
-          rddata_reg(29) <= 'X';
-          rddata_reg(30) <= 'X';
-          rddata_reg(31) <= 'X';
+          rddata_reg(15 downto 0) <= regs_i.dmtd_stat_val_high_i;
+          rddata_reg(31 downto 16) <= regs_i.dmtd_stat_val_low_i;
          ack_sreg(0) <= '1';
          ack_in_progress <= '1';
        when "000111" => 
@@ -768,12 +780,28 @@ regs_o.al_cr_valid_o <= wrdata_reg(8 downto 0);
 -- Aligner required on channel
 -- Aligner reference counter
 -- Aligner reference counter
-- FREQ
+-- SAMPLES
+regs_o.dmtd_stat_cr_samples_o <= spll_dmtd_stat_cr_samples_int;
 -- VALID
-regs_o.f_dmtd_valid_o <= wrdata_reg(28);
-- FREQ
-- VALID
-regs_o.f_ref_valid_o <= wrdata_reg(28);
+-- RST
+process (clk_sys_i, rst_n_i)
+begin
+  if (rst_n_i = '0') then 
+    spll_dmtd_stat_cr_rst_dly0 <= '0';
+    regs_o.dmtd_stat_cr_rst_o <= '0';
+  elsif rising_edge(clk_sys_i) then
+    spll_dmtd_stat_cr_rst_dly0 <= spll_dmtd_stat_cr_rst_int;
+    regs_o.dmtd_stat_cr_rst_o <= spll_dmtd_stat_cr_rst_int and (not spll_dmtd_stat_cr_rst_dly0);
+  end if;
+end process;
+
+
+-- MINMAX_SEL
+regs_o.dmtd_stat_cr_minmax_sel_o <= spll_dmtd_stat_cr_minmax_sel_int;
+-- CHAN_SEL
+regs_o.dmtd_stat_cr_chan_sel_o <= spll_dmtd_stat_cr_chan_sel_int;
+-- HIGH
+-- LOW
 -- FREQ
 -- VALID
 regs_o.f_ext_valid_o <= wrdata_reg(28);

--- a/modules/wr_softpll_ng/spll_wb_slave.wb
+++ b/modules/wr_softpll_ng/spll_wb_slave.wb
@@ -153,48 +153,69 @@ peripheral {
   };
  
 	 reg {
-			name = "DMTD VCO Frequency";
-			prefix = "F_DMTD";
+			name = "DMTD stat control";
+			prefix = "DMTD_STAT_CR";
 			
 			field {
-				 name = "FREQ";
-				 prefix = "FREQ";
+				 name = "SAMPLES";
+				 prefix = "SAMPLES";
 				 type = SLV;
-				 size = 28;
-				 access_bus = READ_ONLY;
-				 access_dev = WRITE_ONLY;
+				 size = 16;
+				 access_bus = READ_WRITE;
+				 access_dev = READ_ONLY;
 			};

 			field {
 				 name = "VALID";
 				 prefix = "VALID";
 				 type = BIT;
+				 access_bus = READ_ONLY;
+				 access_dev = WRITE_ONLY;
+
+			};
+			field {
+				 name = "RST";
+				 prefix = "RST";
+				 type = MONOSTABLE;
+
+			};
+			field {
+				 name = "MINMAX_SEL";
+				 prefix = "MINMAX_SEL";
+				 type = BIT;
 				 access_bus = READ_WRITE;
-				 access_dev = READ_WRITE;
-				 load = LOAD_EXT;
+				 access_dev = READ_ONLY;
+			};
+			field {
+				 name = "CHAN_SEL";
+				 prefix = "CHAN_SEL";
+				 type = SLV;
+				 size = 4;
+				 access_bus = READ_WRITE;
+				 access_dev = READ_ONLY;
 			};
 	 };

 	 reg {
-			name = "REF VCO Frequency";
-			prefix = "F_REF";
+			name = "DMTD stat values";
+			prefix = "DMTD_STAT_VAL";
 			
 			field {
-				 name = "FREQ";
-				 prefix = "FREQ";
+				 name = "HIGH";
+				 prefix = "HIGH";
 				 type = SLV;
-				 size = 28;
+				 size = 16;
 				 access_bus = READ_ONLY;
 				 access_dev = WRITE_ONLY;
 			};

 			field {
-				 name = "VALID";
-				 prefix = "VALID";
-				 type = BIT;
-				 access_bus = READ_WRITE;
-				 access_dev = READ_WRITE;
-				 load = LOAD_EXT;
+				 name = "LOW";
+				 prefix = "LOW";
+				 type = SLV;
+				 size = 16;
+			 	 access_bus = READ_ONLY;
+				 access_dev = WRITE_ONLY;
 			};
 	 };


--- a/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
+++ b/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : spll_wbgen2_pkg.vhd
 -- Author         : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created        : Mon Apr  3 11:13:32 2023
+-- Created        : Thu Jul  6 13:28:58 2023
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
@@ -31,10 +31,9 @@ package spll_wbgen2_pkg is
    al_cr_required_i                         : std_logic_vector(8 downto 0);
    al_cref_i                                : std_logic_vector(31 downto 0);
    al_cin_i                                 : std_logic_vector(31 downto 0);
-    f_dmtd_freq_i                            : std_logic_vector(27 downto 0);
-    f_dmtd_valid_i                           : std_logic;
-    f_ref_freq_i                             : std_logic_vector(27 downto 0);
-    f_ref_valid_i                            : std_logic;
+    dmtd_stat_cr_valid_i                     : std_logic;
+    dmtd_stat_val_high_i                     : std_logic_vector(15 downto 0);
+    dmtd_stat_val_low_i                      : std_logic_vector(15 downto 0);
    f_ext_freq_i                             : std_logic_vector(27 downto 0);
    f_ext_valid_i                            : std_logic;
    occr_out_en_i                            : std_logic_vector(7 downto 0);
@@ -60,10 +59,9 @@ package spll_wbgen2_pkg is
    al_cr_required_i => (others => '0'),
    al_cref_i => (others => '0'),
    al_cin_i => (others => '0'),
-    f_dmtd_freq_i => (others => '0'),
-    f_dmtd_valid_i => '0',
-    f_ref_freq_i => (others => '0'),
-    f_ref_valid_i => '0',
+    dmtd_stat_cr_valid_i => '0',
+    dmtd_stat_val_high_i => (others => '0'),
+    dmtd_stat_val_low_i => (others => '0'),
    f_ext_freq_i => (others => '0'),
    f_ext_valid_i => '0',
    occr_out_en_i => (others => '0'),
@@ -85,10 +83,10 @@ package spll_wbgen2_pkg is
    eccr_ext_ref_pllrst_o                    : std_logic;
    al_cr_valid_o                            : std_logic_vector(8 downto 0);
    al_cr_valid_load_o                       : std_logic;
-    f_dmtd_valid_o                           : std_logic;
-    f_dmtd_valid_load_o                      : std_logic;
-    f_ref_valid_o                            : std_logic;
-    f_ref_valid_load_o                       : std_logic;
+    dmtd_stat_cr_samples_o                   : std_logic_vector(15 downto 0);
+    dmtd_stat_cr_rst_o                       : std_logic;
+    dmtd_stat_cr_minmax_sel_o                : std_logic;
+    dmtd_stat_cr_chan_sel_o                  : std_logic_vector(3 downto 0);
    f_ext_valid_o                            : std_logic;
    f_ext_valid_load_o                       : std_logic;
    occr_out_lock_o                          : std_logic_vector(7 downto 0);
@@ -119,10 +117,10 @@ package spll_wbgen2_pkg is
    eccr_ext_ref_pllrst_o => '0',
    al_cr_valid_o => (others => '0'),
    al_cr_valid_load_o => '0',
-    f_dmtd_valid_o => '0',
-    f_dmtd_valid_load_o => '0',
-    f_ref_valid_o => '0',
-    f_ref_valid_load_o => '0',
+    dmtd_stat_cr_samples_o => (others => '0'),
+    dmtd_stat_cr_rst_o => '0',
+    dmtd_stat_cr_minmax_sel_o => '0',
+    dmtd_stat_cr_chan_sel_o => (others => '0'),
    f_ext_valid_o => '0',
    f_ext_valid_load_o => '0',
    occr_out_lock_o => (others => '0'),
@@ -214,10 +212,9 @@ begin
  tmp.al_cr_required_i := f_x_to_zero(left.al_cr_required_i) or f_x_to_zero(right.al_cr_required_i);
  tmp.al_cref_i := f_x_to_zero(left.al_cref_i) or f_x_to_zero(right.al_cref_i);
  tmp.al_cin_i := f_x_to_zero(left.al_cin_i) or f_x_to_zero(right.al_cin_i);
-  tmp.f_dmtd_freq_i := f_x_to_zero(left.f_dmtd_freq_i) or f_x_to_zero(right.f_dmtd_freq_i);
-  tmp.f_dmtd_valid_i := f_x_to_zero(left.f_dmtd_valid_i) or f_x_to_zero(right.f_dmtd_valid_i);
-  tmp.f_ref_freq_i := f_x_to_zero(left.f_ref_freq_i) or f_x_to_zero(right.f_ref_freq_i);
-  tmp.f_ref_valid_i := f_x_to_zero(left.f_ref_valid_i) or f_x_to_zero(right.f_ref_valid_i);
+  tmp.dmtd_stat_cr_valid_i := f_x_to_zero(left.dmtd_stat_cr_valid_i) or f_x_to_zero(right.dmtd_stat_cr_valid_i);
+  tmp.dmtd_stat_val_high_i := f_x_to_zero(left.dmtd_stat_val_high_i) or f_x_to_zero(right.dmtd_stat_val_high_i);
+  tmp.dmtd_stat_val_low_i := f_x_to_zero(left.dmtd_stat_val_low_i) or f_x_to_zero(right.dmtd_stat_val_low_i);
  tmp.f_ext_freq_i := f_x_to_zero(left.f_ext_freq_i) or f_x_to_zero(right.f_ext_freq_i);
  tmp.f_ext_valid_i := f_x_to_zero(left.f_ext_valid_i) or f_x_to_zero(right.f_ext_valid_i);
  tmp.occr_out_en_i := f_x_to_zero(left.occr_out_en_i) or f_x_to_zero(right.occr_out_en_i);

--- a/modules/wr_softpll_ng/wr_softpll_ng.vhd
+++ b/modules/wr_softpll_ng/wr_softpll_ng.vhd
@@ -79,6 +79,8 @@ entity wr_softpll_ng is
 -- use with care.
    g_divide_input_by_2 : boolean := false;

+    g_with_jitter_stats_regs : boolean := true;
+    
    g_ref_clock_rate : integer := 125_000_000;
    g_ext_clock_rate : integer :=  10_000_000;
    g_sys_clock_rate: integer :=   62_500_000;
@@ -258,6 +260,7 @@ architecture rtl of wr_softpll_ng is
    return tmp;
  end resize;

+
  type t_tag_array is array (0 to f_num_total_channels-1) of std_logic_vector(g_tag_bits-1 downto 0);

  type t_phase_error_array is array(0 to g_num_outputs-1) of std_logic_vector(c_BB_ERROR_BITS-1 downto 0);
@@ -312,6 +315,16 @@ architecture rtl of wr_softpll_ng is
  attribute keep of aligner_sample_cref : signal is "true";
  attribute keep of aligner_sample_cin  : signal is "true";

+  type t_stat_array is array(integer range <>) of std_logic_vector(15 downto 0);
+  
+  signal r_stat_high_ref : t_stat_array(0 to g_num_ref_inputs-1);
+  signal r_stat_low_ref : t_stat_array(0 to g_num_ref_inputs-1);
+  signal r_stat_valid_ref : std_logic_vector(g_num_ref_inputs-1 downto 0);
+  signal r_stat_high_fb : t_stat_array(0 to g_num_outputs-1);
+  signal r_stat_low_fb : t_stat_array(0 to g_num_outputs-1);
+  signal r_stat_valid_fb : std_logic_vector(g_num_outputs-1 downto 0);
+  
+    
 begin  -- rtl

  U_Adapter : wb_slave_adapter
@@ -337,8 +350,6 @@ begin  -- rtl
      sl_ack_o   => wb_ack_o,
      sl_stall_o => wb_stall_o);

-  regs_out.f_dmtd_valid_i <= '0';
-  regs_out.f_ref_valid_i <= '0';
  regs_out.f_ext_valid_i <= '0';

  gen_ref_dmtds : for i in 0 to g_num_ref_inputs-1 generate
@@ -348,6 +359,7 @@ begin  -- rtl
        g_counter_bits      => g_tag_bits,
        g_divide_input_by_2 => g_divide_input_by_2,
        g_reverse	=> g_reverse_dmtds,
+        g_with_jitter_stats_regs => g_with_jitter_stats_regs,
        g_use_sampled_clock => g_use_sampled_ref_clocks)
      port map (
        rst_n_dmtdclk_i => rst_dmtd_n_i,
@@ -363,9 +375,14 @@ begin  -- rtl

        tag_o                => tags(i),
        tag_stb_p1_o         => tags_p(i),
-        r_deglitch_threshold_i => deglitch_thr_slv);
-
-
+        r_deglitch_threshold_i => deglitch_thr_slv,
+        r_low_o => r_stat_low_ref(i),
+        r_high_o => r_stat_high_ref(i),
+        r_samples_i => regs_in.dmtd_stat_cr_samples_o,
+        r_minmax_sel_i => regs_in.dmtd_stat_cr_minmax_sel_o,
+        r_stat_reset_i => regs_in.dmtd_stat_cr_rst_o,
+        r_stat_ready_o => r_stat_valid_ref(i)
+        );
  end generate gen_ref_dmtds;

  gen_feedback_dmtds : for i in 0 to g_num_outputs-1 generate
@@ -379,7 +396,8 @@ begin  -- rtl
        g_divide_input_by_2 => g_divide_input_by_2,
        g_reverse => g_reverse_dmtds,
        g_use_sampled_clock => false,
-        g_with_oversampling => g_aux_config(i).oversample)
+        g_with_jitter_stats_regs => g_with_jitter_stats_regs,
+        g_with_oversampling => g_aux_config(i).oversample )
      port map (
        rst_n_dmtdclk_i => rst_dmtd_n_i,
        rst_n_sysclk_i  => rst_n_i,
@@ -398,7 +416,16 @@ begin  -- rtl

        r_deglitch_threshold_i => deglitch_thr_slv,
        dbg_dmtdout_o        => open,
-        dbg_clk_d3_o         => debug_o(i)); --debug_o(4));
+        dbg_clk_d3_o         => debug_o(i),
+        r_low_o => r_stat_low_fb(i),
+        r_high_o => r_stat_high_fb(i),
+        r_samples_i => regs_in.dmtd_stat_cr_samples_o,
+        r_minmax_sel_i => regs_in.dmtd_stat_cr_minmax_sel_o,
+        r_stat_reset_i => regs_in.dmtd_stat_cr_rst_o,
+        r_stat_ready_o => r_stat_valid_fb(i)
+
+
+        ); --debug_o(4));


  end generate gen_feedback_dmtds;
@@ -412,7 +439,8 @@ begin  -- rtl
      generic map (
        g_counter_bits      => g_tag_bits,
        g_divide_input_by_2 => g_divide_input_by_2,
-        g_reverse	    => g_reverse_dmtds,
+        g_reverse	=> g_reverse_dmtds,
+        g_with_jitter_stats_regs => g_with_jitter_stats_regs,
        g_use_sampled_clock => false)
      port map (
        rst_n_dmtdclk_i => rst_dmtd_n_i,
@@ -428,7 +456,6 @@ begin  -- rtl
        tag_stb_p1_o => tags_p(g_num_ref_inputs + g_num_outputs + I),

        r_deglitch_threshold_i => deglitch_thr_slv);
-
  end generate gen_ext_dmtds;

  gen_with_ext_clock_input: if g_num_exts > 0 generate
@@ -486,6 +513,33 @@ begin  -- rtl
 --    debug_o(5) <= '0';
  end generate gen_without_ext_clock_input;

+
+  p_jitter_stat_regs : process(r_stat_valid_fb, r_stat_valid_ref,
+                               r_stat_high_fb, r_stat_high_ref,
+                               r_stat_low_fb, r_stat_low_ref,
+                               regs_in )
+  begin
+    case regs_in.dmtd_stat_cr_chan_sel_o is
+      when "0000" =>
+        regs_out.dmtd_stat_val_high_i <= r_stat_high_ref(0);
+        regs_out.dmtd_stat_val_low_i <= r_stat_low_ref(0);
+        regs_out.dmtd_stat_cr_valid_i <= r_stat_valid_ref(0);
+      when "0001" =>
+        regs_out.dmtd_stat_val_high_i <= r_stat_high_fb(0);
+        regs_out.dmtd_stat_val_low_i <= r_stat_low_fb(0);
+        regs_out.dmtd_stat_cr_valid_i <= r_stat_valid_fb(0);
+      when "0010" => -- fixme: hack
+        regs_out.dmtd_stat_val_high_i <= r_stat_high_fb(1);
+        regs_out.dmtd_stat_val_low_i <= r_stat_low_fb(1);
+        regs_out.dmtd_stat_cr_valid_i <= r_stat_valid_fb(1);
+      when others =>
+        regs_out.dmtd_stat_cr_valid_i <= '0';
+        regs_out.dmtd_stat_val_low_i <= (others => '0');
+        regs_out.dmtd_stat_val_high_i <= (others => '0');
+    end case;
+  end process;
+  
+
  p_ack_aligner_samples: process(regs_in, aligner_sample_valid)
  begin
    regs_out.al_cr_valid_i <= (others => '0');