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White Rabbit core collection
Commit 6f867f11 authored by Tristan Gingold's avatar Tristan Gingold
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wrc_syscon_wb: add sfp2, add build-date 

Remove unused led_green and led_red, regenerate
Generate H header with struct (instead of offsets)
parent 8feb29dc
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Showing with 472 additions and 317 deletions
modules/wrc_core/build_wb.sh
View file @ 6f867f11
#!/bin/bash
mkdir -p doc
wbgen2 -D ./doc/wrc_syscon.html -p wrc_syscon_pkg.vhd -H record -V wrc_syscon_wb.vhd -C wrc_syscon_regs.h --cstyle defines --lang vhdl -K ../../sim/wrc_syscon_regs.vh wrc_syscon_wb.wb
wbgen2 -D ./doc/wrc_syscon.html -p wrc_syscon_pkg.vhd -H record -V wrc_syscon_wb.vhd -C wrc_syscon_regs.h --cstyle struct --lang vhdl -K ../../sim/wrc_syscon_regs.vh wrc_syscon_wb.wb
wbgen2 -V wrc_cpu_csr_wb.vhd -p wrc_cpu_csr_wbgen2_pkg.vhd --hstyle record_full -Z --lang vhdl -K ../../testbench/wrc_core/wrc_cpu_csr_regs.vh wrc_cpu_csr.wb
modules/wrc_core/wrc_periph.vhd
View file @ 6f867f11
......@@ -268,32 +268,32 @@ begin
-------------------------------------
-- I2C - SFP
-------------------------------------
p_drive_sfpi2c : process(clk_sys_i)
p_drive_sfp1_i2c : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
sfp_scl_o <= '1';
sfp_sda_o <= '1';
else
if(sysc_regs_o.gpsr_sfp_sda_load_o = '1' and sysc_regs_o.gpsr_sfp_sda_o = '1') then
if(sysc_regs_o.gpsr_sfp1_sda_load_o = '1' and sysc_regs_o.gpsr_sfp1_sda_o = '1') then
sfp_sda_o <= '1';
elsif(sysc_regs_o.gpcr_sfp_sda_o = '1') then
elsif(sysc_regs_o.gpcr_sfp1_sda_o = '1') then
sfp_sda_o <= '0';
end if;
if(sysc_regs_o.gpsr_sfp_scl_load_o = '1' and sysc_regs_o.gpsr_sfp_scl_o = '1') then
if(sysc_regs_o.gpsr_sfp1_scl_load_o = '1' and sysc_regs_o.gpsr_sfp1_scl_o = '1') then
sfp_scl_o <= '1';
elsif(sysc_regs_o.gpcr_sfp_scl_o = '1') then
elsif(sysc_regs_o.gpcr_sfp1_scl_o = '1') then
sfp_scl_o <= '0';
end if;
end if;
end if;
end process;
sysc_regs_i.gpsr_sfp_sda_i <= sfp_sda_i;
sysc_regs_i.gpsr_sfp_scl_i <= sfp_scl_i;
sysc_regs_i.gpsr_sfp1_sda_i <= sfp_sda_i;
sysc_regs_i.gpsr_sfp1_scl_i <= sfp_scl_i;
sysc_regs_i.gpsr_sfp_det_i <= sfp_det_i;
sysc_regs_i.gpsr_sfp1_det_i <= sfp_det_i;
-------------------------------------
-- SPI - Flash
......
modules/wrc_core/wrc_syscon_pkg.vhd
View file @ 6f867f11
This diff is collapsed.
modules/wrc_core/wrc_syscon_regs.h
View file @ 6f867f11
......@@ -3,7 +3,7 @@
* File : wrc_syscon_regs.h
* Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
* Created : Mon Mar 28 09:12:03 2022
* Created : Tue Jun 6 11:04:49 2023
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -48,12 +48,6 @@
/* definitions for register: GPIO Set/Readback Register */
/* definitions for field: Status LED in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_LED_STAT WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Link LED in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_LED_LINK WBGEN2_GEN_MASK(1, 1)
/* definitions for field: FMC I2C bitbanged SCL in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_FMC_SCL WBGEN2_GEN_MASK(2, 1)
......@@ -69,14 +63,14 @@
/* definitions for field: SPEC Pushbutton 2 state in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_BTN2 WBGEN2_GEN_MASK(6, 1)
/* definitions for field: SFP detect (MOD_DEF0 signal) in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SFP_DET WBGEN2_GEN_MASK(7, 1)
/* definitions for field: SFP1 detect (MOD_DEF0 signal) in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SFP1_DET WBGEN2_GEN_MASK(7, 1)
/* definitions for field: SFP I2C bitbanged SCL in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SFP_SCL WBGEN2_GEN_MASK(8, 1)
/* definitions for field: SFP1 I2C bitbanged SCL in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SFP1_SCL WBGEN2_GEN_MASK(8, 1)
/* definitions for field: SFP I2C bitbanged SDA in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SFP_SDA WBGEN2_GEN_MASK(9, 1)
/* definitions for field: SFP1 I2C bitbanged SDA in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SFP1_SDA WBGEN2_GEN_MASK(9, 1)
/* definitions for field: SPI bitbanged SCLK in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SPI_SCLK WBGEN2_GEN_MASK(10, 1)
......@@ -90,6 +84,15 @@
/* definitions for field: SPI bitbanged MISO in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SPI_MISO WBGEN2_GEN_MASK(13, 1)
/* definitions for field: SFP2 detect in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SFP2_DET WBGEN2_GEN_MASK(16, 1)
/* definitions for field: SFP2 I2C bitbanged SCL in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SFP2_SCL WBGEN2_GEN_MASK(17, 1)
/* definitions for field: SFP2 I2C bitbanged SDA in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SFP2_SDA WBGEN2_GEN_MASK(18, 1)
/* definitions for register: GPIO Clear Register */
/* definitions for field: Status LED in reg: GPIO Clear Register */
......@@ -105,10 +108,10 @@
#define SYSC_GPCR_FMC_SDA WBGEN2_GEN_MASK(3, 1)
/* definitions for field: SFP I2C bitbanged SCL in reg: GPIO Clear Register */
#define SYSC_GPCR_SFP_SCL WBGEN2_GEN_MASK(8, 1)
#define SYSC_GPCR_SFP1_SCL WBGEN2_GEN_MASK(8, 1)
/* definitions for field: FMC I2C bitbanged SDA in reg: GPIO Clear Register */
#define SYSC_GPCR_SFP_SDA WBGEN2_GEN_MASK(9, 1)
/* definitions for field: SFP I2C bitbanged SDA in reg: GPIO Clear Register */
#define SYSC_GPCR_SFP1_SDA WBGEN2_GEN_MASK(9, 1)
/* definitions for field: SPI bitbanged SCLK in reg: GPIO Clear Register */
#define SYSC_GPCR_SPI_SCLK WBGEN2_GEN_MASK(10, 1)
......@@ -119,6 +122,12 @@
/* definitions for field: SPI bitbanged MOSI in reg: GPIO Clear Register */
#define SYSC_GPCR_SPI_MOSI WBGEN2_GEN_MASK(12, 1)
/* definitions for field: SFP2 I2C bitbanged SCL in reg: GPIO Clear Register */
#define SYSC_GPCR_SFP2_SCL WBGEN2_GEN_MASK(17, 1)
/* definitions for field: SFP2 I2C bitbanged SDA in reg: GPIO Clear Register */
#define SYSC_GPCR_SFP2_SDA WBGEN2_GEN_MASK(18, 1)
/* definitions for register: Hardware Feature Register */
/* definitions for field: Memory size in reg: Hardware Feature Register */
......@@ -214,28 +223,42 @@
#define SYSC_DIAG_CR_RW WBGEN2_GEN_MASK(31, 1)
/* definitions for register: User Diag: data to read/write */
/* [0x0]: REG Syscon reset register */
#define SYSC_REG_RSTR 0x00000000
/* [0x4]: REG GPIO Set/Readback Register */
#define SYSC_REG_GPSR 0x00000004
/* [0x8]: REG GPIO Clear Register */
#define SYSC_REG_GPCR 0x00000008
/* [0xc]: REG Hardware Feature Register */
#define SYSC_REG_HWFR 0x0000000c
/* [0x10]: REG Hardware Info Register */
#define SYSC_REG_HWIR 0x00000010
/* [0x14]: REG Storage SDBFS info */
#define SYSC_REG_SDBFS 0x00000014
/* [0x18]: REG Timer Control Register */
#define SYSC_REG_TCR 0x00000018
/* [0x1c]: REG Timer Counter Value Register */
#define SYSC_REG_TVR 0x0000001c
/* [0x20]: REG User Diag: version register */
#define SYSC_REG_DIAG_INFO 0x00000020
/* [0x24]: REG User Diag: number of words */
#define SYSC_REG_DIAG_NW 0x00000024
/* [0x28]: REG User Diag: Control Register */
#define SYSC_REG_DIAG_CR 0x00000028
/* [0x2c]: REG User Diag: data to read/write */
#define SYSC_REG_DIAG_DAT 0x0000002c
/* definitions for register: HW Build */
/* definitions for field: Date in reg: HW Build */
#define SYSC_HWBLD_DATE_MASK WBGEN2_GEN_MASK(0, 32)
#define SYSC_HWBLD_DATE_SHIFT 0
#define SYSC_HWBLD_DATE_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define SYSC_HWBLD_DATE_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
PACKED struct SYSC_WB {
/* [0x0]: REG Syscon reset register */
uint32_t RSTR;
/* [0x4]: REG GPIO Set/Readback Register */
uint32_t GPSR;
/* [0x8]: REG GPIO Clear Register */
uint32_t GPCR;
/* [0xc]: REG Hardware Feature Register */
uint32_t HWFR;
/* [0x10]: REG Hardware Info Register */
uint32_t HWIR;
/* [0x14]: REG Storage SDBFS info */
uint32_t SDBFS;
/* [0x18]: REG Timer Control Register */
uint32_t TCR;
/* [0x1c]: REG Timer Counter Value Register */
uint32_t TVR;
/* [0x20]: REG User Diag: version register */
uint32_t DIAG_INFO;
/* [0x24]: REG User Diag: number of words */
uint32_t DIAG_NW;
/* [0x28]: REG User Diag: Control Register */
uint32_t DIAG_CR;
/* [0x2c]: REG User Diag: data to read/write */
uint32_t DIAG_DAT;
/* [0x30]: REG HW Build */
uint32_t HWBLD;
};
#endif
modules/wrc_core/wrc_syscon_wb.vhd
View file @ 6f867f11
This diff is collapsed.
modules/wrc_core/wrc_syscon_wb.wb
View file @ 6f867f11
......@@ -9,7 +9,7 @@ peripheral {
reg {
name = "Syscon reset register";
prefix = "RSTR";
field {
name = "Reset trigger";
prefix = "TRIG";
......@@ -17,14 +17,14 @@ peripheral {
type = PASS_THROUGH;
size = 28;
};
field {
name = "Reset line state value";
prefix = "RST";
description = "State of the reset line";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_ONLY;
};
};
......@@ -32,21 +32,6 @@ peripheral {
name = "GPIO Set/Readback Register";
prefix = "GPSR";
field {
name = "Status LED";
description = "Write 1: turn on the Status LED";
prefix = "led_stat";
type = MONOSTABLE;
};
field {
name = "Link LED";
description = "Write 1: turn on the Link LED";
prefix = "led_link";
type = MONOSTABLE;
};
field {
name = "FMC I2C bitbanged SCL";
prefix = "fmc_scl";
......@@ -56,6 +41,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
align = 2;
};
field {
......@@ -67,6 +53,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
align = 3;
};
......@@ -75,6 +62,7 @@ peripheral {
description = "write 1: resets the networking subsystem";
prefix = "Net_RST";
type = MONOSTABLE;
align = 4;
};
field {
......@@ -84,6 +72,7 @@ peripheral {
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
align = 5;
};
field {
......@@ -93,21 +82,23 @@ peripheral {
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
align = 6;
};
field {
name = "SFP detect (MOD_DEF0 signal)";
prefix = "sfp_det";
description = "read : returns the state of the SFP's MOD_DEF0 line";
name = "SFP1 detect (MOD_DEF0 signal)";
prefix = "sfp1_det";
description = "read : returns the state of the SFP1's MOD_DEF0 line";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
align = 7;
};
field {
name = "SFP I2C bitbanged SCL";
prefix = "sfp_scl";
description = "write 1: Set SFP SCL line to 1 (pullup)\
name = "SFP1 I2C bitbanged SCL";
prefix = "sfp1_scl";
description = "write 1: Set SFP1 SCL line to 1 (pullup)\
read : returns the current status of the SCL line.";
type = BIT;
access_bus = READ_WRITE;
......@@ -115,11 +106,11 @@ peripheral {
load = LOAD_EXT;
align = 8;
};
field {
name = "SFP I2C bitbanged SDA";
prefix = "sfp_sda";
description = "write 1: Set SFP SDA line to 1 (pullup)\
name = "SFP1 I2C bitbanged SDA";
prefix = "sfp1_sda";
description = "write 1: Set SFP1 SDA line to 1 (pullup)\
read : returns the current status of the SCL line.";
type = BIT;
access_bus = READ_WRITE;
......@@ -127,7 +118,7 @@ peripheral {
load = LOAD_EXT;
align = 9;
};
field {
name = "SPI bitbanged SCLK";
prefix = "spi_sclk";
......@@ -175,6 +166,40 @@ peripheral {
align = 13;
};
field {
name = "SFP2 detect";
prefix = "sfp2_det";
description = "read : returns the state of the SFP2's MOD_DEF0 line";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
align = 16;
};
field {
name = "SFP2 I2C bitbanged SCL";
prefix = "sfp2_scl";
description = "write 1: Set SFP2 SCL line to 1 (pullup)\
read : returns the current status of the SCL line.";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
align = 17;
};
field {
name = "SFP2 I2C bitbanged SDA";
prefix = "sfp2_sda";
description = "write 1: Set SFP2 SDA line to 1 (pullup)\
read : returns the current status of the SCL line.";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
align = 18;
};
};
reg {
......@@ -186,6 +211,7 @@ peripheral {
description = "Write 1: turn on the Status LED";
prefix = "led_stat";
type = MONOSTABLE;
align = 0;
};
field {
......@@ -193,6 +219,7 @@ peripheral {
description = "Write 1: turn on the Link LED";
prefix = "led_link";
type = MONOSTABLE;
align = 1;
};
field {
......@@ -201,6 +228,7 @@ peripheral {
description = "write 1: Set FMC SCL line to 1 (pullup)\
read : returns the current status of the SCL line.";
type = MONOSTABLE;
align = 2;
};
field {
......@@ -209,19 +237,20 @@ peripheral {
description = "write 1: Set FMC SDA line to 1 (pullup)\
read : returns the current status of the SCL line.";
type = MONOSTABLE;
align = 3;
};
field {
name = "SFP I2C bitbanged SCL";
prefix = "sfp_scl";
prefix = "sfp1_scl";
description = "write 1: Set SFP SCL line to 0.";
type = MONOSTABLE;
align = 8;
};
field {
name = "FMC I2C bitbanged SDA";
prefix = "sfp_sda";
name = "SFP I2C bitbanged SDA";
prefix = "sfp1_sda";
description = "write 1: Set SFP SDA line to 0.";
type = MONOSTABLE;
align = 9;
......@@ -251,6 +280,21 @@ peripheral {
align = 12;
};
field {
name = "SFP2 I2C bitbanged SCL";
prefix = "sfp2_scl";
description = "write 1: Set SFP2 SCL line to 0.";
type = MONOSTABLE;
align = 17;
};
field {
name = "SFP2 I2C bitbanged SDA";
prefix = "sfp2_sda";
description = "write 1: Set SFP2 SDA line to 0.";
type = MONOSTABLE;
align = 18;
};
};
reg {
......@@ -321,14 +365,14 @@ peripheral {
reg {
name = "Storage SDBFS info";
prefix = "SDBFS";
field {
field {
name = "Base address";
prefix = "BADDR";
size = 32;
size = 32;
description = "Default base address in storage, where WRPC should write SDBFS image";
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
......@@ -456,4 +500,17 @@ peripheral {
load = LOAD_EXT;
};
};
reg {
name = "HW Build";
prefix = "HWBLD";
field {
name = "Date";
prefix = "DATE";
size = 32;
description = "Bitstream build date";
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
sim/wrc_syscon_regs.vh
View file @ 6f867f11
......@@ -4,10 +4,6 @@
`define SYSC_RSTR_RST_OFFSET 28
`define SYSC_RSTR_RST 32'h10000000
`define ADDR_SYSC_GPSR 6'h4
`define SYSC_GPSR_LED_STAT_OFFSET 0
`define SYSC_GPSR_LED_STAT 32'h00000001
`define SYSC_GPSR_LED_LINK_OFFSET 1
`define SYSC_GPSR_LED_LINK 32'h00000002
`define SYSC_GPSR_FMC_SCL_OFFSET 2
`define SYSC_GPSR_FMC_SCL 32'h00000004
`define SYSC_GPSR_FMC_SDA_OFFSET 3
......@@ -18,12 +14,12 @@
`define SYSC_GPSR_BTN1 32'h00000020
`define SYSC_GPSR_BTN2_OFFSET 6
`define SYSC_GPSR_BTN2 32'h00000040
`define SYSC_GPSR_SFP_DET_OFFSET 7
`define SYSC_GPSR_SFP_DET 32'h00000080
`define SYSC_GPSR_SFP_SCL_OFFSET 8
`define SYSC_GPSR_SFP_SCL 32'h00000100
`define SYSC_GPSR_SFP_SDA_OFFSET 9
`define SYSC_GPSR_SFP_SDA 32'h00000200
`define SYSC_GPSR_SFP1_DET_OFFSET 7
`define SYSC_GPSR_SFP1_DET 32'h00000080
`define SYSC_GPSR_SFP1_SCL_OFFSET 8
`define SYSC_GPSR_SFP1_SCL 32'h00000100
`define SYSC_GPSR_SFP1_SDA_OFFSET 9
`define SYSC_GPSR_SFP1_SDA 32'h00000200
`define SYSC_GPSR_SPI_SCLK_OFFSET 10
`define SYSC_GPSR_SPI_SCLK 32'h00000400
`define SYSC_GPSR_SPI_NCS_OFFSET 11
......@@ -32,6 +28,12 @@
`define SYSC_GPSR_SPI_MOSI 32'h00001000
`define SYSC_GPSR_SPI_MISO_OFFSET 13
`define SYSC_GPSR_SPI_MISO 32'h00002000
`define SYSC_GPSR_SFP2_DET_OFFSET 16
`define SYSC_GPSR_SFP2_DET 32'h00010000
`define SYSC_GPSR_SFP2_SCL_OFFSET 17
`define SYSC_GPSR_SFP2_SCL 32'h00020000
`define SYSC_GPSR_SFP2_SDA_OFFSET 18
`define SYSC_GPSR_SFP2_SDA 32'h00040000
`define ADDR_SYSC_GPCR 6'h8
`define SYSC_GPCR_LED_STAT_OFFSET 0
`define SYSC_GPCR_LED_STAT 32'h00000001
......@@ -41,16 +43,20 @@
`define SYSC_GPCR_FMC_SCL 32'h00000004
`define SYSC_GPCR_FMC_SDA_OFFSET 3
`define SYSC_GPCR_FMC_SDA 32'h00000008
`define SYSC_GPCR_SFP_SCL_OFFSET 8
`define SYSC_GPCR_SFP_SCL 32'h00000100
`define SYSC_GPCR_SFP_SDA_OFFSET 9
`define SYSC_GPCR_SFP_SDA 32'h00000200
`define SYSC_GPCR_SFP1_SCL_OFFSET 8
`define SYSC_GPCR_SFP1_SCL 32'h00000100
`define SYSC_GPCR_SFP1_SDA_OFFSET 9
`define SYSC_GPCR_SFP1_SDA 32'h00000200
`define SYSC_GPCR_SPI_SCLK_OFFSET 10
`define SYSC_GPCR_SPI_SCLK 32'h00000400
`define SYSC_GPCR_SPI_CS_OFFSET 11
`define SYSC_GPCR_SPI_CS 32'h00000800
`define SYSC_GPCR_SPI_MOSI_OFFSET 12
`define SYSC_GPCR_SPI_MOSI 32'h00001000
`define SYSC_GPCR_SFP2_SCL_OFFSET 17
`define SYSC_GPCR_SFP2_SCL 32'h00020000
`define SYSC_GPCR_SFP2_SDA_OFFSET 18
`define SYSC_GPCR_SFP2_SDA 32'h00040000
`define ADDR_SYSC_HWFR 6'hc
`define SYSC_HWFR_MEMSIZE_OFFSET 0
`define SYSC_HWFR_MEMSIZE 32'h0000000f
......@@ -88,3 +94,6 @@
`define SYSC_DIAG_CR_RW_OFFSET 31
`define SYSC_DIAG_CR_RW 32'h80000000
`define ADDR_SYSC_DIAG_DAT 6'h2c
`define ADDR_SYSC_HWBLD 6'h30
`define SYSC_HWBLD_DATE_OFFSET 0
`define SYSC_HWBLD_DATE 32'hffffffff
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