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White Rabbit core collection
Commit 1ee142a3 authored by Tristan Gingold's avatar Tristan Gingold
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wr_softpll_ng.vhd: minor indentation

parent 91ea0ab0
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    modules/wr_softpll_ng/wr_softpll_ng.vhd
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    ......@@ -6,7 +6,6 @@
    -- Author : Tomasz Włostowski
    -- Company : CERN BE-CO-HT
    -- Created : 2011-01-29
    -- Last update: 2023-04-24
    -- Platform : FPGA-generic
    -- Standard : VHDL'93
    -------------------------------------------------------------------------------
    ......@@ -423,7 +422,7 @@ begin -- rtl
    generic map (
    g_counter_bits => g_tag_bits,
    g_divide_input_by_2 => g_divide_input_by_2,
    g_reverse => g_reverse_dmtds,
    g_reverse => g_reverse_dmtds,
    g_use_sampled_clock => false)
    port map (
    rst_n_dmtdclk_i => rst_dmtd_n_i,
    ......
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