- 27 Jul, 2020 4 commits
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Dimitris Lampridis authored
3.0.0 - 2020-07-27 ================== https://www.ohwr.org/project/gn4124-core/tree/v3.0.0 Added ----- - hdl: SystemVerilog BFM and testbench. - hdl: Add wrapper with wishbone records and slave adapters. - hdl: Add generics to tune the depths of the various async FIFOs. Changed ------- - hdl: Major rewrite of DMA engine, in particular the L2P DMA Master. - hdl: Major cleanup of resets and cross-clock domain synchronisation. - hdl: Stop using coregen FIFOs, switch to FIFOs from general-cores. - hdl: Make DMA optional (g_WITH_DMA generic). - hdl: Use cheby to describe registers, only one interrupt (level). - hdl: Test, verify and enable byte swap feature. - hdl: Extend SV BFM with tasks to read/write from simulated host memory. Fixed ----- - hdl: Fixed incorrect 64-bit DMA transaction generation bug. - hdl: Allow larger DMA reads (up to the full 32 bits of the "length" register) for L2P DMA master. - hdl: Add flow control to the write buffer of the BFM to prevent overflows during 'wr' commands. - hdl: Fix swapped bits in attributes. - hdl: Handle host 32-bit address overflow in L2P DMA master. - hdl: Fix bug in BFM not respecting P2L_RDY during DMA writes. - hdl: Fix bug in BFM not accepting 4096B writes.
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Dimitris Lampridis authored
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Dimitris Lampridis authored
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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Dimitris Lampridis authored
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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- 24 Jul, 2020 8 commits
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Dimitris Lampridis authored
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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Dimitris Lampridis authored
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Dimitris Lampridis authored
Remove the option to use the 200MHz PCI clock for the complete DMA engine to avoid compicating the design and introducing too many alternatives that will need to be tested, now and in the future. On the SPEC, it has been shown that with the latest modifications it is trivial to meet timing when using a 125MHz (asynchronous to the PCI) clock for DMA. Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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Dimitris Lampridis authored
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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Dimitris Lampridis authored
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- 04 Sep, 2019 10 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
Note: P2L DMA already supported this for DMA writes.
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 03 Sep, 2019 2 commits
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Tristan Gingold authored
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Tristan Gingold authored
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- 30 Aug, 2019 1 commit
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Tristan Gingold authored
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- 29 Aug, 2019 2 commits
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Tristan Gingold authored
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Dimitris Lampridis authored
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- 28 Aug, 2019 1 commit
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Tristan Gingold authored
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- 23 Aug, 2019 3 commits
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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- 08 Aug, 2019 4 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 07 Aug, 2019 1 commit
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Dimitris Lampridis authored
[hdl] fix bug in new dma_controller where the DMA status was not properly exposed through the WB registers
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- 06 Aug, 2019 2 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 05 Aug, 2019 1 commit
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Dimitris Lampridis authored
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- 01 Aug, 2019 1 commit
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Tristan Gingold authored
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