Commit 8cf1d41b authored by Dimitris Lampridis's avatar Dimitris Lampridis

hdl: remove g_DMA_USE_PCI_CLK option

Remove the option to use the 200MHz PCI clock for the complete DMA engine to avoid compicating the design
and introducing too many alternatives that will need to be tested, now and in the future.

On the SPEC, it has been shown that with the latest modifications it is trivial to meet timing when using
a 125MHz (asynchronous to the PCI) clock for DMA.
Signed-off-by: Dimitris Lampridis's avatarDimitris Lampridis <dimitris.lampridis@cern.ch>
parent b11363a3
This diff is collapsed.
......@@ -42,9 +42,8 @@ use work.genram_pkg.all;
entity p2l_dma_master is
generic (
g_DMA_USE_PCI_CLK : boolean := FALSE;
g_FIFO_SIZE : positive := 64;
g_BYTE_SWAP : boolean := FALSE);
g_FIFO_SIZE : positive := 64;
g_BYTE_SWAP : boolean := FALSE);
port (
---------------------------------------------------------
-- GN4124 core clock and reset
......@@ -194,6 +193,9 @@ architecture arch of p2l_dma_master is
signal next_item_next_h : std_logic_vector(31 downto 0) := (others => '0');
signal next_item_attrib : std_logic_vector(31 downto 0) := (others => '0');
signal to_wb_fifo_full_d : std_logic_vector(c_SYNC_FIFO_FULL_DELAY - 1 downto 0) := (others => '0');
signal to_wb_fifo_full_next : std_logic;
begin
......@@ -517,82 +519,54 @@ begin
------------------------------------------------------------------------------
fifo_rst_n <= rst_n_i;
gen_sync_fifo : if g_DMA_USE_PCI_CLK = TRUE generate
begin
wb_fifo_rst_n <= fifo_rst_n;
cmp_to_wb_fifo : generic_sync_fifo
generic map (
g_DATA_WIDTH => 64,
g_SIZE => g_FIFO_SIZE,
g_SHOW_AHEAD => TRUE,
g_WITH_COUNT => FALSE)
port map (
rst_n_i => fifo_rst_n,
clk_i => clk_i,
-- write port
d_i => to_wb_fifo_din_d,
we_i => to_wb_fifo_wr_d,
full_o => to_wb_fifo_full,
-- read port
q_o => to_wb_fifo_dout,
rd_i => to_wb_fifo_rd,
empty_o => to_wb_fifo_empty);
end generate gen_sync_fifo;
gen_async_fifo : if g_DMA_USE_PCI_CLK = FALSE generate
signal to_wb_fifo_full_d : std_logic_vector(c_SYNC_FIFO_FULL_DELAY - 1 downto 0) := (others => '0');
signal to_wb_fifo_full_next : std_logic;
-- Local resynced copy of fifo_rst_n to make sure that both sides of the fifo
-- are reset if rst_n_i = '0'
cmp_wb_fifo_rst_sync : gc_sync
port map (
clk_i => wb_dma_clk_i,
rst_n_a_i => wb_dma_rst_n_i,
d_i => fifo_rst_n,
q_o => wb_fifo_rst_n);
-- Pipeline to_wb_fifo_full to help with timing. This requires the
-- equivalent setting in g_ALMOST_FULL_THRESHOLD to prevent overflows.
p_fifo_full_delay_reg : process (wb_dma_clk_i) is
begin
-- Local resynced copy of fifo_rst_n to make sure that both sides of the fifo
-- are reset if rst_n_i = '0'
cmp_wb_fifo_rst_sync : gc_sync
port map (
clk_i => wb_dma_clk_i,
rst_n_a_i => wb_dma_rst_n_i,
d_i => fifo_rst_n,
q_o => wb_fifo_rst_n);
-- Pipeline to_wb_fifo_full to help with timing. This requires the
-- equivalent setting in g_ALMOST_FULL_THRESHOLD to prevent overflows.
p_fifo_full_delay_reg : process (wb_dma_clk_i) is
begin
if rising_edge(wb_dma_clk_i) then
-- we want proper registers to help with timing and
-- having a reset prevents inferring of shift register.
if wb_fifo_rst_n = '0' then
to_wb_fifo_full_d <= (others => '0');
else
to_wb_fifo_full_d <= to_wb_fifo_full_d(to_wb_fifo_full_d'high-1 downto 0) & to_wb_fifo_full_next;
end if;
if rising_edge(wb_dma_clk_i) then
-- we want proper registers to help with timing and
-- having a reset prevents inferring of shift register.
if wb_fifo_rst_n = '0' then
to_wb_fifo_full_d <= (others => '0');
else
to_wb_fifo_full_d <= to_wb_fifo_full_d(to_wb_fifo_full_d'high-1 downto 0) & to_wb_fifo_full_next;
end if;
end process p_fifo_full_delay_reg;
to_wb_fifo_full <= to_wb_fifo_full_d(to_wb_fifo_full_d'high);
cmp_to_wb_fifo : generic_async_fifo_dual_rst
generic map (
g_DATA_WIDTH => 64,
g_SIZE => g_FIFO_SIZE,
g_SHOW_AHEAD => TRUE,
g_WITH_WR_FULL => FALSE,
g_WITH_WR_ALMOST_FULL => TRUE,
-- 20 less to give time to the GN4124 to react to P2L_RDY going low.
g_ALMOST_FULL_THRESHOLD => g_FIFO_SIZE - c_SYNC_FIFO_FULL_DELAY - 20)
port map (
-- write port
rst_wr_n_i => fifo_rst_n,
clk_wr_i => clk_i,
d_i => to_wb_fifo_din_d,
we_i => to_wb_fifo_wr_d,
wr_almost_full_o => to_wb_fifo_full_next,
-- read port
rst_rd_n_i => wb_fifo_rst_n,
clk_rd_i => wb_dma_clk_i,
q_o => to_wb_fifo_dout,
rd_i => to_wb_fifo_rd,
rd_empty_o => to_wb_fifo_empty);
end generate gen_async_fifo;
end if;
end process p_fifo_full_delay_reg;
to_wb_fifo_full <= to_wb_fifo_full_d(to_wb_fifo_full_d'high);
cmp_to_wb_fifo : generic_async_fifo_dual_rst
generic map (
g_DATA_WIDTH => 64,
g_SIZE => g_FIFO_SIZE,
g_SHOW_AHEAD => TRUE,
g_WITH_WR_FULL => FALSE,
g_WITH_WR_ALMOST_FULL => TRUE,
-- 20 less to give time to the GN4124 to react to P2L_RDY going low.
g_ALMOST_FULL_THRESHOLD => g_FIFO_SIZE - c_SYNC_FIFO_FULL_DELAY - 20)
port map (
-- write port
rst_wr_n_i => fifo_rst_n,
clk_wr_i => clk_i,
d_i => to_wb_fifo_din_d,
we_i => to_wb_fifo_wr_d,
wr_almost_full_o => to_wb_fifo_full_next,
-- read port
rst_rd_n_i => wb_fifo_rst_n,
clk_rd_i => wb_dma_clk_i,
q_o => to_wb_fifo_dout,
rd_i => to_wb_fifo_rd,
rd_empty_o => to_wb_fifo_empty);
-- pause transfer from GN4124 if fifo is (almost) full
p2l_rdy_o <= not(to_wb_fifo_full);
......
......@@ -41,11 +41,6 @@ entity gn4124_core is
generic (
-- If TRUE, enable the DMA interface
g_WITH_DMA : boolean := TRUE;
-- if TRUE, use 200MHz PCI clock also for DMA transfers.
-- if FALSE, use whatever is provided by the user on dma_clk_i,
-- which is assumed to be asynchronous to the PCI clock and goes
-- through dual clock FIFOs.
g_DMA_USE_PCI_CLK : boolean := FALSE;
-- Tunable size and threshold for all async FIFOs.
-- If not sure, leave the defaults.
g_WBM_TO_WB_FIFO_SIZE : positive := 128;
......@@ -62,11 +57,6 @@ entity gn4124_core is
rst_n_a_i : in std_logic; -- Asynchronous reset from GN4124
status_o : out std_logic_vector(31 downto 0); -- Core status output
---------------------------------------------------------
-- 200MHz PCI clock output and synchronous reset for applications
clk_200m_o : out std_logic;
rst_200m_n_o : out std_logic;
---------------------------------------------------------
-- P2L Direction
--
......@@ -178,9 +168,6 @@ architecture rtl of gn4124_core is
signal sys_rst_n : std_logic;
signal arst_pll : std_logic;
signal wb_dma_clk : std_logic;
signal wb_dma_rst_n : std_logic;
-------------------------------------------------------------
-- P2L DataPath (from deserializer to packet decoder)
-------------------------------------------------------------
......@@ -351,9 +338,6 @@ begin
clks_i(0) => sys_clk,
rst_n_o(0) => sys_rst_n);
clk_200m_o <= sys_clk;
rst_200m_n_o <= sys_rst_n;
-- Always active high reset for PLL and SERDES
arst_pll <= not(rst_n_a_i);
......@@ -362,19 +346,6 @@ begin
------------------------------------------------------------------------------
irq_p_o <= irq_p_i;
------------------------------------------------------------------------------
-- DMA WB clock and reset selection
------------------------------------------------------------------------------
gen_sync_wb_dma : if g_DMA_USE_PCI_CLK = TRUE generate
wb_dma_clk <= sys_clk;
wb_dma_rst_n <= sys_rst_n;
end generate gen_sync_wb_dma;
gen_async_wb_dma : if g_DMA_USE_PCI_CLK = FALSE generate
wb_dma_clk <= dma_clk_i;
wb_dma_rst_n <= dma_rst_n_i;
end generate gen_async_wb_dma;
--============================================================================
-- P2L DataPath
--============================================================================
......@@ -598,9 +569,8 @@ begin
-----------------------------------------------------------------------------
cmp_l2p_dma_master : entity work.l2p_dma_master
generic map (
g_DMA_USE_PCI_CLK => g_DMA_USE_PCI_CLK,
g_FIFO_SIZE => g_L2P_FIFO_SIZE,
g_BYTE_SWAP => TRUE)
g_FIFO_SIZE => g_L2P_FIFO_SIZE,
g_BYTE_SWAP => TRUE)
port map (
clk_i => sys_clk,
rst_n_i => sys_rst_n,
......@@ -626,8 +596,8 @@ begin
l2p_rdy_i => l2p_rdy,
tx_error_i => tx_error,
wb_dma_rst_n_i => wb_dma_rst_n,
wb_dma_clk_i => wb_dma_clk,
wb_dma_rst_n_i => dma_rst_n_i,
wb_dma_clk_i => dma_clk_i,
wb_dma_i => l2p_dma_in,
wb_dma_o => l2p_dma_out);
......@@ -640,9 +610,8 @@ begin
-----------------------------------------------------------------------------
cmp_p2l_dma_master : entity work.p2l_dma_master
generic map (
g_DMA_USE_PCI_CLK => g_DMA_USE_PCI_CLK,
g_FIFO_SIZE => g_P2L_FIFO_SIZE,
g_BYTE_SWAP => TRUE)
g_FIFO_SIZE => g_P2L_FIFO_SIZE,
g_BYTE_SWAP => TRUE)
port map (
clk_i => sys_clk,
rst_n_i => sys_rst_n,
......@@ -678,8 +647,8 @@ begin
pdm_arb_req_o => pdm_arb_req,
arb_pdm_gnt_i => arb_pdm_gnt,
wb_dma_rst_n_i => wb_dma_rst_n,
wb_dma_clk_i => wb_dma_clk,
wb_dma_rst_n_i => dma_rst_n_i,
wb_dma_clk_i => dma_clk_i,
wb_dma_i => p2l_dma_in,
wb_dma_o => p2l_dma_out,
......
......@@ -10,7 +10,7 @@
-- Spartan6 FPGAs version.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2010-2018
-- Copyright CERN 2010-2020
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
......@@ -56,7 +56,6 @@ package gn4124_core_pkg is
component xwb_gn4124_core is
generic (
g_WITH_DMA : boolean := TRUE;
g_DMA_USE_PCI_CLK : boolean := FALSE;
g_WBM_TO_WB_FIFO_SIZE : positive := 128;
g_WBM_TO_WB_FIFO_FULL_THRES : positive := 110;
g_WBM_FROM_WB_FIFO_SIZE : positive := 128;
......@@ -73,8 +72,6 @@ package gn4124_core_pkg is
port (
rst_n_a_i : in std_logic;
status_o : out std_logic_vector(31 downto 0);
clk_200m_o : out std_logic;
rst_200m_n_o : out std_logic;
p2l_clk_p_i : in std_logic;
p2l_clk_n_i : in std_logic;
p2l_data_i : in std_logic_vector(15 downto 0);
......@@ -116,7 +113,6 @@ package gn4124_core_pkg is
component gn4124_core
generic (
g_WITH_DMA : boolean := TRUE;
g_DMA_USE_PCI_CLK : boolean := FALSE;
g_WBM_TO_WB_FIFO_SIZE : positive := 128;
g_WBM_TO_WB_FIFO_FULL_THRES : positive := 110;
g_WBM_FROM_WB_FIFO_SIZE : positive := 128;
......@@ -130,11 +126,6 @@ package gn4124_core_pkg is
rst_n_a_i : in std_logic; -- Asynchronous reset from GN4124
status_o : out std_logic_vector(31 downto 0); -- Core status output
---------------------------------------------------------
-- 200MHz PCI clock output and synchronous reset for applications
clk_200m_o : out std_logic;
rst_200m_n_o : out std_logic;
---------------------------------------------------------
-- P2L Direction
--
......
......@@ -34,11 +34,6 @@ entity xwb_gn4124_core is
generic (
-- If TRUE, enable the DMA interface
g_WITH_DMA : boolean := TRUE;
-- if TRUE, use 200MHz PCI clock also for DMA transfers.
-- if FALSE, use whatever is provided by the user on dma_clk_i,
-- which is assumed to be asynchronous to the PCI clock and goes
-- through dual clock FIFOs.
g_DMA_USE_PCI_CLK : boolean := FALSE;
-- Tunable size and threshold for all async FIFOs.
-- If not sure, leave the defaults.
g_WBM_TO_WB_FIFO_SIZE : positive := 128;
......@@ -62,11 +57,6 @@ entity xwb_gn4124_core is
rst_n_a_i : in std_logic; -- Asynchronous reset from GN4124
status_o : out std_logic_vector(31 downto 0); -- Core status output
---------------------------------------------------------
-- 200MHz PCI clock output and synchronous reset for applications
clk_200m_o : out std_logic;
rst_200m_n_o : out std_logic;
---------------------------------------------------------
-- P2L Direction
--
......@@ -197,7 +187,6 @@ begin
cmp_wrapped_gn4124 : gn4124_core
generic map (
g_WITH_DMA => g_WITH_DMA,
g_DMA_USE_PCI_CLK => g_DMA_USE_PCI_CLK,
g_WBM_TO_WB_FIFO_SIZE => g_WBM_TO_WB_FIFO_SIZE,
g_WBM_TO_WB_FIFO_FULL_THRES => g_WBM_TO_WB_FIFO_FULL_THRES,
g_WBM_FROM_WB_FIFO_SIZE => g_WBM_FROM_WB_FIFO_SIZE,
......@@ -208,8 +197,6 @@ begin
port map (
rst_n_a_i => rst_n_a_i,
status_o => status_o,
clk_200m_o => clk_200m_o,
rst_200m_n_o => rst_200m_n_o,
p2l_clk_p_i => p2l_clk_p_i,
p2l_clk_n_i => p2l_clk_n_i,
p2l_data_i => p2l_data_i,
......
......@@ -65,14 +65,9 @@ module main;
IGN4124PCIMaster i_gn4124 ();
xwb_gn4124_core #
(
.g_dma_use_pci_clk (0)
)
xwb_gn4124_core
DUT (
.rst_n_a_i (i_gn4124.rst_n),
.clk_200m_o (clk_gn4124),
.rst_200m_n_o (rst_gn4124_n),
.p2l_clk_p_i (i_gn4124.p2l_clk_p),
.p2l_clk_n_i (i_gn4124.p2l_clk_n),
.p2l_data_i (i_gn4124.p2l_data),
......@@ -111,16 +106,8 @@ module main;
.wb_dma_dat_o (wb_dma_out)
);
/* -----\/----- EXCLUDED -----\/-----
assign wb_dma_clk = clk_gn4124;
assign wb_dma_rst_n = rst_gn4124_n;
-----/\----- EXCLUDED -----/\----- */
assign wb_dma_clk = clk_125m;
assign wb_dma_rst_n = rst_125m_n;
/* -----\/----- EXCLUDED -----\/-----
assign wb_dma_clk = clk_62m5;
assign wb_dma_rst_n = rst_62m5_n;
-----/\----- EXCLUDED -----/\----- */
xwb_dpram #
(
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment