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Gennum GN4124 core
Commit e7637624 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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SPDX-License-Identifier: CC0-1.0
SPDX-FileCopyrightText: 2019-2020 CERN
==========
Change Log
==========
- Format inspired by: `Keep a Changelog <https://keepachangelog.com/en/1.0.0/>`_
- Versioning scheme follows: `Semantic Versioning <https://semver.org/spec/v2.0.0.html>`_
3.0.0 - 2020-07-27
==================
https://www.ohwr.org/project/gn4124-core/tree/v3.0.0
Added
-----
- hdl: SystemVerilog BFM and testbench.
- hdl: Add wrapper with wishbone records and slave adapters.
- hdl: Add generics to tune the depths of the various async FIFOs.
Changed
-------
- hdl: Major rewrite of DMA engine, in particular the L2P DMA Master.
- hdl: Major cleanup of resets and cross-clock domain synchronisation.
- hdl: Stop using coregen FIFOs, switch to FIFOs from general-cores.
- hdl: Make DMA optional (g_WITH_DMA generic).
- hdl: Use cheby to describe registers, only one interrupt (level).
- hdl: Test, verify and enable byte swap feature.
- hdl: Extend SV BFM with tasks to read/write from simulated host memory.
Fixed
-----
- hdl: Fixed incorrect 64-bit DMA transaction generation bug.
- hdl: Allow larger DMA reads (up to the full 32 bits of the "length" register) for L2P DMA master.
- hdl: Add flow control to the write buffer of the BFM to prevent overflows during 'wr' commands.
- hdl: Fix swapped bits in attributes.
- hdl: Handle host 32-bit address overflow in L2P DMA master.
- hdl: Fix bug in BFM not respecting P2L_RDY during DMA writes.
- hdl: Fix bug in BFM not accepting 4096B writes.
2.0.0 - 2014-04-03
==================
https://www.ohwr.org/project/gn4124-core/tree/v2.0.0
Added
-----
- Second release of gn4124-core
1.0.0 - 2013-03-01
==================
https://www.ohwr.org/project/gn4124-core/tree/v1.0.0
Added
-----
- First release of gn4124-core
LICENCES/LICENSE.CC0-1_0 0 → 100644
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LICENCES/LICENSE.SHL-2_0 0 → 100644
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# Solderpad Hardware Licence Version 2.0
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Manifest.py
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if target=="xilinx":
modules = {
"local" : [
"hdl/gn4124core/rtl",
"hdl/rtl",
],
}
if action == "simulation":
modules['local'].append("hdl/gn4124core/sim/gn4124_bfm")
modules['local'].append("hdl/sim/gn4124_bfm")
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hdl/gn4124core/sim/example_tb/main.sv deleted 100644 → 0
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//------------------------------------------------------------------------------
// CERN BE-CO-HT
// GN4124 core for PCIe FMC carrier
// http://www.ohwr.org/projects/gn4124-core
//------------------------------------------------------------------------------
//
// unit name: main
//
// description: This is a simple example testbench, to demonstrate how to use
// the SystemVerilog BFM of the GN4124 to perform simple accesses over wishbone.
//
// The testbench simply connects the wishbone master of the GN4124 to its own
// DMA configuration wishbone slave and attaches a pre-initialised dummy RAM
// with a wishbone interface to the pipelined DMA interface in order to perform
// a DMA read.
//
//------------------------------------------------------------------------------
// Copyright CERN 2019
//------------------------------------------------------------------------------
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 2.0 (the "License"); you may not use this file except
// in compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-2.0.
// Unless required by applicable law or agreed to in writing, software,
// hardware and materials distributed under this License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
// or implied. See the License for the specific language governing permissions
// and limitations under the License.
//------------------------------------------------------------------------------
`timescale 1ns/1ps
`include "gn4124_bfm.svh"
import wishbone_pkg::*;
module main;
reg clk_125m = 0;
logic gn4124_irq;
t_wishbone_master_in wb_in, wb_dma_in, wb_mem_in;
t_wishbone_master_out wb_out, wb_dma_out, wb_mem_out;
always #4ns clk_125m <= ~clk_125m;
logic rst_125m_n;
initial begin
rst_125m_n = 0;
#80ns rst_125m_n = 1;
end
IGN4124PCIMaster i_gn4124 ();
xwb_gn4124_core
DUT (
.rst_n_a_i (i_gn4124.rst_n),
.p2l_clk_p_i (i_gn4124.p2l_clk_p),
.p2l_clk_n_i (i_gn4124.p2l_clk_n),
.p2l_data_i (i_gn4124.p2l_data),
.p2l_dframe_i (i_gn4124.p2l_dframe),
.p2l_valid_i (i_gn4124.p2l_valid),
.p2l_rdy_o (i_gn4124.p2l_rdy),
.p_wr_req_i (i_gn4124.p_wr_req),
.p_wr_rdy_o (i_gn4124.p_wr_rdy),
.rx_error_o (i_gn4124.rx_error),
.vc_rdy_i (i_gn4124.vc_rdy),
.l2p_clk_p_o (i_gn4124.l2p_clk_p),
.l2p_clk_n_o (i_gn4124.l2p_clk_n),
.l2p_data_o (i_gn4124.l2p_data),
.l2p_dframe_o (i_gn4124.l2p_dframe),
.l2p_valid_o (i_gn4124.l2p_valid),
.l2p_edb_o (i_gn4124.l2p_edb),
.l2p_rdy_i (i_gn4124.l2p_rdy),
.l_wr_rdy_i (i_gn4124.l_wr_rdy),
.p_rd_d_rdy_i (i_gn4124.p_rd_d_rdy),
.tx_error_i (i_gn4124.tx_error),
.dma_irq_o (),
.irq_p_i (1'b0),
.irq_p_o (gn4124_irq),
.status_o (),
.wb_master_clk_i (clk_125m),
.wb_master_rst_n_i (rst_125m_n),
.wb_master_i (wb_in),
.wb_master_o (wb_out),
.wb_dma_cfg_clk_i (clk_125m),
.wb_dma_cfg_rst_n_i (rst_125m_n),
.wb_dma_cfg_i (wb_out),
.wb_dma_cfg_o (wb_in),
.wb_dma_dat_clk_i (clk_125m),
.wb_dma_dat_rst_n_i (rst_125m_n),
.wb_dma_dat_i (wb_dma_in),
.wb_dma_dat_o (wb_dma_out)
);
xwb_dpram #
(
.g_size (32),
.g_init_file ("mem_init.bram"),
.g_slave1_interface_mode (1), // 1 = PIPELINED
.g_slave2_interface_mode (1),
.g_slave1_granularity (1), // 1 = WORD
.g_slave2_granularity (1)
)
MEM (
.rst_n_i (1'b1),
.clk_sys_i (clk_125m),
.slave1_i (wb_dma_out),
.slave1_o (wb_dma_in),
.slave2_i (wb_mem_out),
.slave2_o (wb_mem_in)
);
CBusAccessor acc;
task val_check(string name, uint64_t addr, val, expected);
if (val != expected)
begin
$display();
$display("Simulation FAILED");
$fatal(1, "%s error at address 0x%.2x. Expected 0x%.8x, got 0x%.8x",
name, addr, expected, val);
end
$display("%s at address 0x%.2x: 0x%.8x [OK]",
name, addr, val);
endtask // val_check
task reg_check(uint64_t addr, expected);
uint64_t val;
acc.read(addr, val);
val_check("Register read-back", addr, val, expected);
endtask // reg_check
initial begin
uint64_t addr, val, expected;
@(posedge i_gn4124.ready);
acc = i_gn4124.get_accessor();
acc.set_default_xfer_size(4);
@(posedge clk_125m);
// Verify simple read/writes over wishbone
reg_check('h0, 'h0);
acc.write('h10, 'hffacce55);
acc.write('h20, 'h1badcafe);
reg_check('h10, 'hffacce55);
reg_check('h20, 'h1badcafe);
// Reset all DMA config registers
for (addr = 'h00; addr <= 'h20; addr += 4)
begin
acc.write(addr, 'h0);
end
// Perform 32 reads over DMA
acc.write('h14, 'h80);
acc.write('h00, 'h01);
// Check values read from memory
@(posedge i_gn4124.l2p_valid); // skip header
@(posedge i_gn4124.l2p_valid);
for (addr = 'h20; addr > 'h00; addr -= 1)
begin
expected = 64'h80000000 + addr - 1;
val = i_gn4124.l2p_data;
@(posedge i_gn4124.l2p_clk_n);
val |= i_gn4124.l2p_data << 16;
val_check("DMA read-back", 'h20-addr, val, expected);
@(posedge i_gn4124.l2p_clk_p);
end
#1us;
$display();
$display("Simulation PASSED");
$finish;
end
endmodule // main
hdl/gn4124core/sim/example_tb/mem_init.bram deleted 100644 → 0
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10000000000000000000000000011111
10000000000000000000000000011110
10000000000000000000000000011101
10000000000000000000000000011100
10000000000000000000000000011011
10000000000000000000000000011010
10000000000000000000000000011001
10000000000000000000000000011000
10000000000000000000000000010111
10000000000000000000000000010110
10000000000000000000000000010101
10000000000000000000000000010100
10000000000000000000000000010011
10000000000000000000000000010010
10000000000000000000000000010001
10000000000000000000000000010000
10000000000000000000000000001111
10000000000000000000000000001110
10000000000000000000000000001101
10000000000000000000000000001100
10000000000000000000000000001011
10000000000000000000000000001010
10000000000000000000000000001001
10000000000000000000000000001000
10000000000000000000000000000111
10000000000000000000000000000110
10000000000000000000000000000101
10000000000000000000000000000100
10000000000000000000000000000011
10000000000000000000000000000010
10000000000000000000000000000001
10000000000000000000000000000000
hdl/gn4124core/wb_gen/dma_controller_wb_slave.wb deleted 100644 → 0
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--------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- GN4124 core for PCIe FMC carrier
-- http://www.ohwr.org/projects/gn4124-core
--------------------------------------------------------------------------------
--
-- unit name: dma_controller_wb_slave
--
-- description: GN4124 core DMA controller registers block layout (wbgen2)
--
--------------------------------------------------------------------------------
-- Copyright CERN 2010-2018
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
peripheral {
name = "GN4124 core DMA controller ";
description = "Wishbone slave for the DMA controller of the GN4124 core";
hdl_entity = "dma_controller_wb_slave";
prefix = "dma";
reg {
name = "DMACTRLR";
prefix = "ctrl";
field {
name = "DMA engine control";
type = SLV;
size = 32;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
clock = "clk_i"
};
};
reg {
name = "DMASTATR";
prefix = "stat";
field {
name = "DMA engine status";
type = SLV;
size = 32;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
clock = "clk_i"
};
};
reg {
name = "DMACSTARTR";
prefix = "cstart";
field {
name = "DMA start address in the carrier";
type = SLV;
size = 32;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
clock = "clk_i"
};
};
reg {
name = "DMAHSTARTLR";
prefix = "hstartl";
field {
name = "DMA start address (low) in the host";
type = SLV;
size = 32;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
clock = "clk_i"
};
};
reg {
name = "DMAHSTARTHR";
prefix = "hstarth";
field {
name = "DMA start address (high) in the host";
type = SLV;
size = 32;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
clock = "clk_i"
};
};
reg {
name = "DMALENR";
prefix = "len";
field {
name = "DMA read length in bytes";
type = SLV;
size = 32;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
clock = "clk_i"
};
};
reg {
name = "DMANEXTLR";
prefix = "nextl";
field {
name = "Pointer (low) to next item in list";
type = SLV;
size = 32;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
clock = "clk_i"
};
};
reg {
name = "DMANEXTHR";
prefix = "nexth";
field {
name = "Pointer (high) to next item in list";
type = SLV;
size = 32;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
clock = "clk_i"
};
};
reg {
name = "DMAATTRIBR";
prefix = "attrib";
field {
name = "DMA chain control";
type = SLV;
size = 32;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
clock = "clk_i"
};
};
};
general-cores @ 258eb8e0
Subproject commit 4e5f7badf0b72f51bdb01c63fcdc6d69afb4b750
Subproject commit 258eb8e00f99f795fe9b98840b01ac4a8b92ec94
hdl/gn4124core/rtl/Manifest.py → hdl/rtl/Manifest.py
View file @ e7637624
files = [
"dma_controller.vhd",
"dma_controller_wb_slave.vhd",
"dma_controller_regs.vhd",
"l2p_arbiter.vhd",
"l2p_dma_master.vhd",
"p2l_decode32.vhd",
......
hdl/rtl/dma_controller.vhd 0 → 100644
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hdl/rtl/dma_controller_regs.cheby 0 → 100644
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# ------------------------------------------------------------------------------
# CERN BE-CO-HT
# GN4124 core for PCIe FMC carrier
# http://www.ohwr.org/projects/gn4124-core
# ------------------------------------------------------------------------------
#
# unit name: dma_controller_regs
#
# description: GN4124 core DMA controller registers block layout
#
# ------------------------------------------------------------------------------
# Copyright CERN 2010-2019
# ------------------------------------------------------------------------------
# Copyright and related rights are licensed under the Solderpad Hardware
# License, Version 2.0 (the "License"); you may not use this file except
# in compliance with the License. You may obtain a copy of the License at
# http://solderpad.org/licenses/SHL-2.0.
# Unless required by applicable law or agreed to in writing, software,
# hardware and materials distributed under this License is distributed on an
# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
# or implied. See the License for the specific language governing permissions
# and limitations under the License.
# ------------------------------------------------------------------------------
memory-map:
bus: wb-32-be
name: dma_controller_regs
description: "GN4124 core DMA controller"
comment: Wishbone slave for the DMA controller of the GN4124 core
children:
- reg:
name: ctrl
address: 0x00000000
width: 32
access: rw
description: DMACTRLR
children:
- field:
name: start
range: 0
comment: Start DMA transfer
description: Write '1' to start a DMA transfer