update of axi_wb_i2c_master modules because of tricell errors resulting in broken i2c; still to be done for wrc

fasec_hwtest module bugfix; set_registers tcl script changed because of out of context IPs; after synthesis

fasec_hwtest and wrc_1p_kintex7 modules updated for WR debugging and FMC hardware tests with PS interrupts

design uses submodules only (instead of HDD repo); wrpc links some debug clocks to fasec_hwmodule for debugging

after reimportation, synthesis and implementation OK; still work needed on timing constraints though

design goes succesfully through synthesis and implementation; timing constraints not met caused by clk_fpga_1 - ext. 10 MHz - which should not cause problems