after reimportation, synthesis and implementation OK; still work needed on...
after reimportation, synthesis and implementation OK; still work needed on timing constraints though
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- FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd 137 additions, 0 deletions..._0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd
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- FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_xadc_wiz_0_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_design_xadc_wiz_0_0_address_decoder.vhd 496 additions, 0 deletions...l/src/vhdl/system_design_xadc_wiz_0_0_address_decoder.vhd
- FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_xadc_wiz_0_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_design_xadc_wiz_0_0_axi_lite_ipif.vhd 300 additions, 0 deletions...hdl/src/vhdl/system_design_xadc_wiz_0_0_axi_lite_ipif.vhd
- FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_xadc_wiz_0_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_design_xadc_wiz_0_0_slave_attachment.vhd 520 additions, 0 deletions.../src/vhdl/system_design_xadc_wiz_0_0_slave_attachment.vhd
- FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_xadc_wiz_0_0/interrupt_control_v2_01_a/hdl/src/vhdl/system_design_xadc_wiz_0_0_interrupt_control.vhd 1396 additions, 0 deletions...src/vhdl/system_design_xadc_wiz_0_0_interrupt_control.vhd
- FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/system_design_xadc_wiz_0_0_conv_funs_pkg.vhd 289 additions, 0 deletions...hdl/src/vhdl/system_design_xadc_wiz_0_0_conv_funs_pkg.vhd
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