fasec_hwtest module bugfix; set_registers tcl script changed because of out of... (2ec6201a) · Commits · Projects / FPGA and ARM SoC FMC Carrier FASEC

Commit 2ec6201a authored 7 years ago by

Pieter Van Trappen

fasec_hwtest module bugfix; set_registers tcl script changed because of out of...

fasec_hwtest module bugfix; set_registers tcl script changed because of out of context IPs; after synthesis

parent 2f398cc1

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.Xil/Vivado-27812-lapte24154/coregen/clock_temp/clock_temp.xci 44 additions, 0 deletions

...Vivado-27812-lapte24154/coregen/clock_temp/clock_temp.xci
.Xil/Vivado-27812-lapte24154/coregen/clock_temp/clock_temp.xml 91 additions, 0 deletions

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FASEC_prototype.ip_user_files/bd/system_design/hdl/system_design.vhd 1 addition, 1 deletion

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FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_dma_0_0/system_design_axi_dma_0_0_sim_netlist.v 31325 additions, 0 deletions

...esign_axi_dma_0_0/system_design_axi_dma_0_0_sim_netlist.v
FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_dma_0_0/system_design_axi_dma_0_0_sim_netlist.vhdl 34945 additions, 0 deletions

...gn_axi_dma_0_0/system_design_axi_dma_0_0_sim_netlist.vhdl
FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_uartlite_0_0/system_design_axi_uartlite_0_0_sim_netlist.v 3773 additions, 0 deletions

...uartlite_0_0/system_design_axi_uartlite_0_0_sim_netlist.v
FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_uartlite_0_0/system_design_axi_uartlite_0_0_sim_netlist.vhdl 3824 additions, 0 deletions

...tlite_0_0/system_design_axi_uartlite_0_0_sim_netlist.vhdl
FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.v 4068 additions, 0 deletions

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FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.vhdl 4880 additions, 0 deletions

..._0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.vhdl
FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.v 4068 additions, 0 deletions

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FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.vhdl 4880 additions, 0 deletions

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FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd 2 additions, 2 deletions

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FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_processing_system7_0_0/system_design_processing_system7_0_0_sim_netlist.v 5420 additions, 0 deletions

...m7_0_0/system_design_processing_system7_0_0_sim_netlist.v
FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_processing_system7_0_0/system_design_processing_system7_0_0_sim_netlist.vhdl 4615 additions, 0 deletions

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FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_rst_processing_system7_0_100M_2/system_design_rst_processing_system7_0_100M_2_sim_netlist.v 935 additions, 0 deletions

...stem_design_rst_processing_system7_0_100M_2_sim_netlist.v
FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_rst_processing_system7_0_100M_2/system_design_rst_processing_system7_0_100M_2_sim_netlist.vhdl 1079 additions, 0 deletions

...m_design_rst_processing_system7_0_100M_2_sim_netlist.vhdl
FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/system_design_rst_wrc_1p_kintex7_0_62M_0_sim_netlist.v 935 additions, 0 deletions

..._0/system_design_rst_wrc_1p_kintex7_0_62M_0_sim_netlist.v
FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/system_design_rst_wrc_1p_kintex7_0_62M_0_sim_netlist.vhdl 1079 additions, 0 deletions

...system_design_rst_wrc_1p_kintex7_0_62M_0_sim_netlist.vhdl
FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/system_design_wrc_1p_kintex7_0_0_sim_netlist.v 156897 additions, 0 deletions

...intex7_0_0/system_design_wrc_1p_kintex7_0_0_sim_netlist.v
FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/system_design_wrc_1p_kintex7_0_0_sim_netlist.vhdl 181433 additions, 0 deletions

...ex7_0_0/system_design_wrc_1p_kintex7_0_0_sim_netlist.vhdl

with 444294 additions and 3 deletions

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