commiting files from after synthesis, uart was not a hardware problem in the end
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- FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.hwdef 0 additions, 0 deletions...e.srcs/sources_1/bd/system_design/hdl/system_design.hwdef
- FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.vhd 6 additions, 11 deletions...ype.srcs/sources_1/bd/system_design/hdl/system_design.vhd
- FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd 1 addition, 1 deletion.../sources_1/bd/system_design/hdl/system_design_wrapper.vhd
- FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design.hwh 18 additions, 26 deletions...s/sources_1/bd/system_design/hw_handoff/system_design.hwh
- FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design_bd.tcl 76 additions, 80 deletions...ources_1/bd/system_design/hw_handoff/system_design_bd.tcl
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.xml 5 additions, 5 deletions...gn/ip/system_design_auto_pc_0/system_design_auto_pc_0.xml
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.xml 5 additions, 5 deletions...gn/ip/system_design_auto_pc_1/system_design_auto_pc_1.xml
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v 2 additions, 2 deletions.../hdl/verilog/processing_system7_v5_5_processing_system7.v
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_processing_system7_0_0/hdl/verilog/system_design_processing_system7_0_0.hwdef 0 additions, 0 deletions..._0/hdl/verilog/system_design_processing_system7_0_0.hwdef
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_processing_system7_0_0/ps7_init.c 24 additions, 204 deletions...design/ip/system_design_processing_system7_0_0/ps7_init.c
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_processing_system7_0_0/ps7_init.html 817 additions, 3176 deletions...ign/ip/system_design_processing_system7_0_0/ps7_init.html
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_processing_system7_0_0/ps7_init.tcl 6 additions, 18 deletions...sign/ip/system_design_processing_system7_0_0/ps7_init.tcl
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_processing_system7_0_0/ps7_init_gpl.c 24 additions, 204 deletions...gn/ip/system_design_processing_system7_0_0/ps7_init_gpl.c
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_processing_system7_0_0/ps7_parameters.xml 3 additions, 3 deletions...p/system_design_processing_system7_0_0/ps7_parameters.xml
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v 0 additions, 4 deletions...ng_system7_0_0/sim/system_design_processing_system7_0_0.v
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_processing_system7_0_0/synth/system_design_processing_system7_0_0.v 2 additions, 8 deletions..._system7_0_0/synth/system_design_processing_system7_0_0.v
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_processing_system7_0_0/system_design_processing_system7_0_0.xdc 3 additions, 3 deletions...sing_system7_0_0/system_design_processing_system7_0_0.xdc
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_processing_system7_0_0/system_design_processing_system7_0_0.xml 11 additions, 11 deletions...sing_system7_0_0/system_design_processing_system7_0_0.xml
- FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v2_9/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd 2 additions, 2 deletions...c_hwtest_v2_9/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
- FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bd 412 additions, 2 deletions...rototype.srcs/sources_1/bd/system_design/system_design.bd
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