after synthesis (96664c9d) · Commits · Projects / FPGA and ARM SoC FMC Carrier FASEC · GitLab

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FPGA and ARM SoC FMC Carrier FASEC
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96664c9d

Commit 96664c9d authored 7 years ago by

Pieter Van Trappen

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after synthesis

parent f38fc372

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Changes 9

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FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.dcp 0 additions, 0 deletions

...esign_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.dcp
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xml 1 addition, 1 deletion

...esign_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xml
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_sim_netlist.v 397 additions, 397 deletions

...c_hwtest_0_0/system_design_fasec_hwtest_0_0_sim_netlist.v
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_sim_netlist.vhdl 395 additions, 395 deletions

...wtest_0_0/system_design_fasec_hwtest_0_0_sim_netlist.vhdl
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_stub.v 1 addition, 1 deletion

...gn_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_stub.v
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_stub.vhdl 1 addition, 1 deletion

...fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_stub.vhdl
FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd 2 additions, 2 deletions

...hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
FASEC_prototype.xpr 2 additions, 1 deletion

FASEC_prototype.xpr
firmware/system_design_wrapper.bit 0 additions, 0 deletions

firmware/system_design_wrapper.bit

with 799 additions and 798 deletions

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