update of axi_wb_i2c_master modules because of tricell errors resulting in... (f08bde95) · Commits · Projects / FPGA and ARM SoC FMC Carrier FASEC

Commit f08bde95 authored 7 years ago by

Pieter Van Trappen

update of axi_wb_i2c_master modules because of tricell errors resulting in...

update of axi_wb_i2c_master modules because of tricell errors resulting in broken i2c; still to be done for wrc

parent 2ec6201a

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.Xil/Vivado-27812-lapte24154/coregen/clock_temp/clock_temp.xci 0 additions, 44 deletions

...Vivado-27812-lapte24154/coregen/clock_temp/clock_temp.xci
.Xil/Vivado-27812-lapte24154/coregen/clock_temp/clock_temp.xml 0 additions, 91 deletions

...Vivado-27812-lapte24154/coregen/clock_temp/clock_temp.xml
FASEC_prototype.ip_user_files/bd/system_design/hdl/system_design.vhd 47 additions, 47 deletions

...type.ip_user_files/bd/system_design/hdl/system_design.vhd
FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd 2 additions, 2 deletions

...2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd
FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.v 0 additions, 4068 deletions

...ter_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.v
FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.vhdl 0 additions, 4880 deletions

..._0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.vhdl
FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd 2 additions, 2 deletions

...2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd
FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.v 0 additions, 4068 deletions

...ter_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.v
FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.vhdl 0 additions, 4880 deletions

..._2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.vhdl
FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd 0 additions, 0 deletions

...r_v3_1_2/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd
FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd 0 additions, 0 deletions

..._v3_1_2/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd
FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/clockDivider.vhd 0 additions, 0 deletions

..._v3_1_2/ip_cores/hdl_lib/modules/general/clockDivider.vhd
FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/counterUpDown.vhd 0 additions, 0 deletions

...v3_1_2/ip_cores/hdl_lib/modules/general/counterUpDown.vhd
FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd 0 additions, 0 deletions

..._v3_1_2/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd
FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd 0 additions, 0 deletions

...1_2/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd
FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd 0 additions, 0 deletions

...2/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd
FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/shiftRegister.vhd 0 additions, 0 deletions

...v3_1_2/ip_cores/hdl_lib/modules/general/shiftRegister.vhd
FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd 0 additions, 0 deletions

..._1_2/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd
FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/main_pkg.vhd 0 additions, 0 deletions

...b_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/main_pkg.vhd
FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/axis_to_i2c_wbs.vhd 29 additions, 10 deletions

...n.ch/axi_wb_i2c_master_v3_1_2/modules/axis_to_i2c_wbs.vhd

with 80 additions and 18092 deletions

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