after synthesis, I should really start putting timing constraints.. (953715ab) · Commits · Projects / FPGA and ARM SoC FMC Carrier FASEC · GitLab

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FPGA and ARM SoC FMC Carrier FASEC
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953715ab

Commit 953715ab authored 7 years ago by

Pieter Van Trappen

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after synthesis, I should really start putting timing constraints..

parent e3139120

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Changes 6

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.Xil/Vivado-3878-lapte24154/coregen/clock_temp_1/clock_temp.xci 44 additions, 0 deletions

...ivado-3878-lapte24154/coregen/clock_temp_1/clock_temp.xci
.Xil/Vivado-3878-lapte24154/coregen/clock_temp_1/clock_temp.xml 91 additions, 0 deletions

...ivado-3878-lapte24154/coregen/clock_temp_1/clock_temp.xml
FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd 3 additions, 2 deletions

...hwtest_v3_2_2/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
FASEC_prototype.srcs/tcl/set_registers.tcl 6 additions, 1 deletion

FASEC_prototype.srcs/tcl/set_registers.tcl
FASEC_prototype.xpr 22 additions, 13 deletions

FASEC_prototype.xpr
firmware/system_design_wrapper.bit 0 additions, 0 deletions

firmware/system_design_wrapper.bit

with 166 additions and 16 deletions

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