wrpc updated to v2.3.1: new lm32 software, word access of wrpc memory without addr*4 requirement (32628e8a) · Commits · Projects / FPGA and ARM SoC FMC Carrier FASEC

Commit 32628e8a authored 8 years ago by

Pieter Van Trappen

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wrpc updated to v2.3.1: new lm32 software, word access of wrpc memory without addr*4 requirement

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FASEC_prototype.ip_user_files/bd/system_design/hdl/system_design.vhd 63 additions, 63 deletions

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FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd 2 additions, 2 deletions

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FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd 2 additions, 2 deletions

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FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd 2 additions, 2 deletions

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FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd 0 additions, 0 deletions

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FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd 11 additions, 4 deletions

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FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd 0 additions, 0 deletions

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FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd 0 additions, 0 deletions

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FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd 0 additions, 0 deletions

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FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd 0 additions, 0 deletions

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FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd 0 additions, 0 deletions

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FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/shiftRegister.vhd 0 additions, 0 deletions

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FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd 0 additions, 0 deletions

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FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/main_pkg.vhd 3 additions, 2 deletions

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FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/axis_to_i2c_wbs.vhd 3 additions, 2 deletions

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FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_bit_ctrl.vhd 0 additions, 0 deletions

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FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_byte_ctrl.vhd 0 additions, 0 deletions

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FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/sim/axis_to_i2c_wbs_tb.vhd 0 additions, 0 deletions

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